Chip packaging structure
A chip packaging structure with better reliability includes a first protective layer, a redistribution layer formed on the first protective layer, at least one chip electrically connected to the redistribution layer, and an encapsulating layer covering the redistribution layer, the chip, and the side surfaces of the first protective layer. The first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface. A plurality of second openings is defined in the second protective layer, and a portion of the redistribution layer is exposed from the plurality of second openings.
1. A chip packaging structure comprising:
a first protective layer, wherein the first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface;
a redistribution layer formed on the first protective layer;
a second protective layer covering the redistribution layer;
at least one chip electrically connected to the redistribution layer; and
an encapsulating layer covering the second protective layer, the chip, and the at least four side surfaces of the first protective layer;
wherein the encapsulating layer is made of epoxy resin.
2. The chip packaging structure of claim 1 , wherein a plurality of first openings is defined in the first protective layer, a portion of the redistribution layer is exposed from the plurality of first openings, the chip packaging structure further comprises a plurality of solder balls, and each of the plurality of solder balls is formed in one of the plurality of first openings.
3. The chip packaging structure of claim 1 , wherein a plurality of second openings is defined in the second protective layer, a portion of the redistribution layer is exposed from the plurality of second openings, and a plurality of contact pads are formed in the plurality of second openings; each of the plurality of contact pads is formed in each of the plurality of second openings.
4. The chip packaging structure of claim 3 , wherein the at least one chip comprises a second surface, the second surface faces is parallel to the second protective layer, a plurality of conductive bumps is formed on the second surface, the plurality of conductive bumps is fixed on the plurality of electrical contact pads, each of the plurality of conductive bumps corresponds to each of the plurality of contact pads.
5. The chip packaging structure of claim 1 , wherein the encapsulating layer comprises a sealing surface, the sealing surface is coplanar with the exposed surface of the first protective layer.