FinFET cut isolation opening revision to compensate for overlay inaccuracy

1. A method, comprising:

for an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout:

determining a number of fins to be cut with same source/drain connection by a fin cut isolation opening;

determining a fin cut isolation pitch in a gate length direction of the plurality of gates to each side of the fin cut isolation opening; and

revising a size of the fin cut isolation opening in the IC layout based on the number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction.

2. The method of claim 1 , wherein for each selected side of the fin cut isolation opening in a respected fin, the revising includes:

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being two and the fin cut isolation pitch in the gate length direction being greater than two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 0.5 nanometers; or

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being two and the fin cut isolation pitch in the gate length direction being less than or equal to two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 1.0 nanometers.

3. The method of claim 1 , wherein for each selected side of the fin cut isolation opening in a respected fin, the revising includes:

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being one and the fin cut isolation pitch in the gate length direction being greater than two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 1.0 nanometers; or

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being one and the fin cut isolation pitch in the gate length direction adjacent the selected side being less than or equal to two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 1.5 nanometers.

4. The method of claim 3 , wherein for each selected side of the fin cut isolation opening in a respected fin, the revising includes:

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being two and the fin cut isolation pitch in the gate length direction adjacent the selected side being greater than two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 0.5 nanometers; or

in response to the number of fins to be cut with same source/drain connection by the fin cut isolation opening being two and the fin cut isolation pitch in the gate length direction adjacent the selected side being less than or equal to two, moving the selected side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening by up to 1.0 nanometers.

5. The method of claim 1 , wherein the revising includes moving at least one side of the fin cut isolation opening in the IC layout to reduce a width of the fin cut isolation opening.

6. The method of claim 5 , wherein a first side of the fin cut isolation opening is moved more than a second, opposing side of the fin cut isolation opening to reduce the width of the fin cut isolation opening more on the first side than on the second, opposing side.

7. The method of claim 6 , wherein the first side is closer to an adjacent fin cut isolation in which the fin cut isolation pitch in the gate length direction is smaller.

8. The method of claim 1 , further comprising performing optical proximity correction on the IC layout for the active region in the reticle.

9. An integrated circuit (IC) structure, comprising:

a plurality of semiconductor fins on a substrate;

a first fin-type field effect transistor (finFETs) using at least one of the semiconductor fins;

a second fin-type field effect transistor (finFETs) on the substrate and adjacent the first finFET, the second finFET using more semiconductor fins than the first finFET but sharing at least one semiconductor fin with the first finFET;

a first fin cut isolation segregating the at least one shared semiconductor fin between the first and second finFET, the first fin cut isolation having a first width; and

a second fin cut isolation segregating the at least one shared semiconductor fin of the first finFET from at least one third finFET, the second fin cut isolation having a second width,

wherein the first and second width are within 1.0 nanometers of one another.

10. The IC structure of claim 9 , wherein a first gate of the first finFET has a third width, and a second gate of the second finFET has a fourth width, wherein the third width is greater than the fourth width.

11. The IC structure of claim 9 , wherein each fin cut isolation is narrower where the fin cut isolation intersects a respective fin compared to where the fin cut isolation extends between fins.