Encoder and decoder for memory system and method thereof

1. A system comprising:

a memory device including multiple level cells; and

a controller including an encoder suitable for:

generating a plurality of random sequences and scrambling data bits corresponding to a logical page, selected from among multiple logical pages, using the plurality of random sequences, to generate a plurality of scrambled sequences;

selecting, as an encoded sequence, a scrambled sequence among the plurality of scrambled sequences; and

providing the memory device with the encoded sequence to store the encoded sequence in the multiple level cells,

wherein the selected scrambled sequence has the lowest number of logical high values among the plurality of scrambled sequences.

2. The system of claim 1 , wherein the encoder includes:

a plurality of random generators suitable for generating the plurality of random sequences;

a plurality of scramblers suitable for scrambling the data bits to generate the plurality of scrambled sequences, using the plurality of random sequences, wherein each of the plurality of scramblers scrambles the data bits, using the corresponding random sequence among the plurality of random sequences; and

a selector suitable for selecting, as the encoded sequence, the scrambled sequence having the lowest number of logical high values among the plurality of scrambled sequences,

wherein the encoder includes a plurality of encoding components, each of the plurality of encoding components including a corresponding random generator among the plurality of random generators and a corresponding scrambler among the plurality of scramblers.

3. The system of claim 2 , wherein each of the plurality of scramblers scrambles the data bits by performing an XOR operation on the data bits with a corresponding random sequence among the plurality of random sequences.

4. The system of claim 3 , wherein the multiple level cells include triple-level cells (TLCs), and the multiple logical pages include a most significant bit (MSB) page, a center significant bit (CSB) page and a least significant bit (LSB) page.

5. The system of claim 4 , wherein the selected logical page includes the MSB page.

6. The system of claim 4 , wherein the selected logical page includes a logical page having a ratio of a first probability to a second probability that is greater than a threshold value, the first probability indicating a probability of a logical high value stored in the memory device being incorrectly read as a logical low value, and the second probability indicating a probability of a logical low value stored in the memory device being incorrectly read as a logical high value.

7. The system of claim 4 , wherein the encoder further includes a plurality of counters suitable for outputting a plurality of counted values,

each of the plurality of counters suitable for counting the number of the logical high value in a corresponding scrambled sequence among the plurality of scrambled sequences, to output a corresponding counted value, and

each of the plurality of encoding components including a corresponding counter among the plurality of counters.

8. The system of claim 4 , wherein the selector includes:

a first selection component suitable for receiving the plurality of counted values, selecting the lowest counted value among the plurality of counted values and outputting, to the memory device, indication information indicating a random sequence among the plurality of random sequences, corresponding to the lowest counted value; and

a second selection component suitable for receiving the plurality of scrambled sequences, selecting the encoded sequence based on the indication information and outputting, to the memory device, the encoded sequence.

9. The system of claim 4 , further comprising:

a first encoding component suitable for encoding the data bits using a cyclic redundancy check (CRC) code, and outputting the encoded data bits to each of the plurality of encoding components; and

a second encoding component suitable for receiving the encoded sequence, encoding the encoded sequence using a low density parity check (LDPC) code and outputting the LDPC encoded sequence to the memory device.

10. A system comprising:

a memory device including multiple level cells, in which an encoded sequence is stored; and

a controller including a decoder suitable for:

generating a plurality of random sequences;

receiving, from the memory device, the encoded sequence and indication information;

selecting a random sequence among the plurality of random sequences, based on the indication information; and

descrambling the encoded sequence using the selected random sequence to generate a descrambled sequence as data bits corresponding to a logical page, selected from among multiple logical pages,

wherein the indication information indicates the random sequence corresponding to a scrambled sequence having a lowest number of logical high values, among a plurality of scrambled sequences, which is generated by scrambling the data bits using the plurality of random sequences.

11. The system of claim 10 , wherein the decoder includes:

a plurality of random generators suitable for generating the plurality of random sequences;

a plurality of descramblers; and

a selector suitable for selecting a random generator among the plurality of random generators and a descrambler among the plurality of descramblers, based on the indication information, such that the selected descrambler descrambles the encoded sequence using a corresponding random sequence generated by the selected random generator,

wherein the decoder includes a plurality of decoding components, each of the plurality of decoding components including a corresponding random generator among the plurality of random generators and a corresponding descrambler among the plurality of descramblers.

12. The system of claim 10 , wherein the selected descrambler descrambles the encoded sequence by performing an XOR operation on the encoded sequence with the selected random sequence.

13. The system of claim 12 , wherein the multiple level cells include triple-level cells (TLCs), and the multiple logical pages include a most significant bit (MSB) page, a center significant bit (CSB) page and a least significant bit (LSB) page.

14. The system of claim 13 , wherein the selected logical page includes the MSB page.

15. The system of claim 13 , wherein the selected logical page includes a logical page having a ratio of a first probability to a second probability that is greater than a threshold value, the first probability indicating a probability of a logical high value stored in the memory device being incorrectly read as a logical low value, and the second probability indicating a probability of a logical low value stored in the memory device being incorrectly read as a logical high value.

16. A system comprising:

a memory device including multiple level cells, in which an encoded sequence is stored; and

a controller including a decoder suitable for:

receiving, from the memory device, the encoded sequence;

decoding the encoded sequence using a low density parity check (LDPC) code to generate an LDPC decoded sequence;

generating a plurality of random sequences;

descrambling the LDPC decoded sequence using the plurality of random sequences, to generate a plurality of descrambled sequences; and

selecting a descrambled sequence to be recovered, among the plurality of descrambled sequences, based on cyclic redundancy check (CRC) syndromes of the plurality of descrambled sequences, to generate a recovered sequence including data bits corresponding to a logical page, selected from among multiple logical pages,

wherein the selected descrambled sequence has the lowest number of logical high values, among a plurality of scrambled sequences, which were generated by scrambling the data bits using the plurality of random sequences.

17. The system of claim 16 , wherein the decoder includes:

a plurality of random generators suitable for generating the plurality of random sequences;

a plurality of descramblers suitable for descrambling the LDPC decoded sequence using the plurality of random sequences, to generate the plurality of descrambled sequences, wherein each of the plurality of descramblers descrambles the LDPC decoded sequence, using the corresponding random sequence; and

a selector suitable for selecting the descrambled sequence based on the CRC syndromes,

wherein the decoder includes a plurality of decoding components, each including a corresponding random generator among the plurality of random generators and a corresponding descrambler among the plurality of descramblers.

18. The system of claim 17 , wherein each of the plurality of descramblers descrambles the LDPC decoded sequence by performing an XOR operation on the LDPC decoded sequence with a corresponding random sequence among the plurality of random sequences.

19. The system of claim 18 , wherein the multiple level cells include triple-level cells (TLCs), and the multiple logical pages include a most significant bit (MSB) page, a center significant bit (CSB) page and a least significant bit (LSB) page.

20. The system of claim 19 , wherein the selected logical page includes the MSB page.

21. The system of claim 19 , wherein the selected logical page includes a logical page having a ratio of a first probability to a second probability that is greater than a threshold value, the first probability indicating a probability of a logical high value stored in the memory device being incorrectly read as a logical low value, and the second probability indicating a probability of a logical low value stored in the memory device being incorrectly read as a logical high value.

22. The system of claim 19 , wherein the decoder further includes a plurality of calculators suitable for calculating the CRC syndromes of the plurality of descrambled sequences,

each of the plurality of calculators suitable for calculating a corresponding CRC syndrome among the CRC syndromes, and

each of the plurality of decoding components including a corresponding calculator among the plurality of calculators.

23. The system of claim 22 , wherein the selector includes:

a first selection component suitable for receiving the CRC syndromes, selecting a CRC syndrome among the CRC syndromes, the selected CRC syndrome having a value of zero, and outputting indication information indicating the selected CRC syndrome; and

a second selection component suitable for receiving the plurality of descrambled sequences, selecting the descrambled sequence among the plurality of descrambled sequences based on the indication information and outputting the selected descrambled sequence as the recovered sequence.