Neighbor assisted correction error recovery for memory system and method thereof
Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.
1. A system comprising:
a memory device including a plurality of cells; and
a controller suitable for:
performing a read on a cell among the plurality of cells; and
adjusting a log-likelihood ratio (LLR) value on the cell to generate an adjusted LLR value, based on first read data on the cell and second read data on at least one neighbor cell adjacent to the cell, when the read on the cell fails.
2. The system of claim 1 , wherein the controller performs a decoding operation on the first read data using the adjusted LLR value.
3. The system of claim 1 , wherein each of the plurality of cells includes one of a triple-level cell (TLC) and a quadruple-level cell (QLC).
4. The system of claim 1 , wherein the at least one neighbor cell includes at least one of an upper cell and a lower cell, which are adjacent to the cell, and
wherein the at least one upper cell and lower cell and the cell share a same bit line, and word lines of the upper cell, the lower cell and the cell are adjacent to each other.
5. The system of claim 1 , wherein the controller includes:
an LLR value generator suitable for generating the LLR value on the cell; and
an LLR value adjuster suitable for:
receiving the LLR value;
generating a compensation value using the first read data and the second read data; and
adjusting the LLR value based on the compensation value to generate the adjusted LLR value.
6. The system of claim 5 , wherein the LLR value adjuster includes:
a compensation value generator suitable for receiving the first read data and the second read data, and generating the compensation value based on a data pattern of the first read data and the second read data; and
an adjusting component suitable for receiving the LLR value, and adjusting the LLR value based on the compensation value to generate the adjusted LLR value.
7. The system of claim 6 , wherein the compensation value generator generates the compensation value based on a data pattern of the first read data and the second read data and the number of unsatisfied checks connected to each bit values of the first read data.
8. The system of claim 6 , wherein the adjusting component generates the adjusted LLR value by adding the compensation value to the LLR value.
9. The system of claim 6 , wherein the adjusting component generates the adjusted LLR value by multiplying the LLR value by the compensation value.
10. The system of claim 1 , wherein the controller includes a buffer for storing the second read data, and
the controller performs the adjusting of the LLR value when the second read data is stored in the buffer or a retention time of the first read data is high.
11. A method for operating a memory system including a memory device including a plurality of cells, the method comprising:
performing a read on a cell among the plurality of cells; and
when the read on the cell fails, adjusting a log-likelihood ratio (LLR) value on the cell to generate an adjusted LLR value, based on first read data on the cell and second read data on at least one neighbor cell adjacent to the cell.
12. The method of claim 11 , further comprising: performing a decoding operation on the first read data using the adjusted LLR value.
13. The method of claim 11 , wherein each of the plurality of cells includes one of a triple-level cell (TLC) and a quadruple-level cell (QLC).
14. The method of claim 11 , wherein the at least one neighbor cell includes at least one of an upper cell and a lower cell, which are adjacent to the cell, and
wherein the at least one upper cell and lower cell and the cell share a same bit line, and word lines of the upper cell, the lower cell and the cell are adjacent to each other.
15. The method of claim 11 , wherein the adjusting of the LLR value includes:
generating an LLR value on the cell;
generating a compensation value using the first read data and the second read data; and
adjusting the LLR value based on the compensation value to generate the adjusted LLR value.
16. The method of claim 15 , wherein the generating of the compensation value includes:
generating the compensation value based on a data pattern of the first read data and the second read data.
17. The method of claim 16 , wherein the generating of the compensation value includes:
generating the compensation value based on a data pattern of the first read data and the second read data and the number of unsatisfied checks connected to each bit values of the first read data.
18. The method of claim 16 , wherein the adjusting of the value of the LLR includes adding the compensation value to the LLR value.
19. The method of claim 16 , wherein the adjusting of the value of the LLR includes multiplying the LLR value by the compensation value.
20. The method of claim 11 , wherein the adjusting of the LLR value is performed when the second read data is stored in a buffer or a retention time of the first read data is high.