Memory system with deep learning based interference correction capability and method of operating such memory system
Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.
1. A memory controller, comprising:
a decoder configured to perform first soft decoding to generate log-likelihood ratio (LLR) values of a bit and bits of memory cells neighboring a memory cell of the bit; and
a quantizer configured to obtain an estimated LLR value of the bit based on the LLR values of the bit and the bits of the memory cells neighboring the memory cell of the bit, when the first soft decoding fails, wherein
the decoder is further configured to
perform second soft decoding using the estimated LLR value, when the first soft decoding fails, and
perform third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the bit, when the second soft decoding fails.
2. The memory controller of claim 1 , wherein the decoder performs the third soft decoding to provide the more accurate estimate of the LLR value of the bit based on information on the bits of the memory cells neighboring the memory cell of the bit that is generated by the decoder in the second soft decoding.
3. The memory controller of claim 2 , wherein the deep learning model is trained on failed bits.
4. The memory controller of claim 3 , the deep learning model is based on a function that minimizes cross-entropy between a genie LLR for the bit and an output of the function.
5. The memory controller of claim 1 , wherein the quantizer is optimized based on code information for the bit.
6. The memory controller of claim 5 , wherein the code information includes a number of unsatisfied checks connected to the bit and degree of the bit.
7. The memory controller of claim 5 , wherein the quantizer is optimized by maximizing information between a variable denoting a correct input value for the bit and a variable representing a range of desired quantized values for the decoder.
8. The memory controller of claim 1 , wherein the decoder is further configured to perform hard decoding before performing the first soft decoding.
9. The memory controller of claim 1 , wherein the decoder comprises a low-density parity-check (LDPC) decoder.
10. A memory system, comprising:
a memory device including a memory cell array of memory cells formed at intersections of bit lines and word lines; and
a memory controller comprising
a decoder configured to perform first soft decoding to generate log-likelihood ratio (LLR) values of a bit and bits of memory cells neighboring a memory cell of the bit, and
a quantizer configured to obtain an estimated LLR value of the bit based on the LLR values of the bit and the bits of the memory cells neighboring the memory cell of the bit, when the first soft decoding fails, wherein
the decoder is further configured to
perform second soft decoding using the estimated LLR value, when the first soft decoding fails, and
perform third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the bit, when the second soft decoding fails.
11. A method of decoding, the method comprising:
performing first soft decoding of a codeword to generate log-likelihood ratio (LLR) values of a bit and bits of memory cells neighboring a memory cell of the bit;
applying interference correction to obtain an estimated LLR value of the bit using information on the bits of the memory cells neighboring the memory cell of the bit obtained during the first soft decoding, when the first soft decoding fails;
performing second soft decoding of the codeword using the estimated LLR value obtained by applying interference correction;
applying a deep learning model to provide a more accurate estimate of the LLR value of the bit when the second decoding fails; and
performing third soft decoding of the codeword using the more accurate estimated LLR value of the bit obtained by applying the deep learning model.
12. The method of claim 11 , wherein the third soft decoding to obtain the more accurate estimate of the LLR value of the bit is performed based on information on the bits of the memory cells neighboring the memory cell of the bit that is generated in the performing of the second soft decoding.
13. The method of claim 11 , wherein the interference correction is applied using an optimized quantizer.
14. The method of claim 13 , further comprising:
optimizing the quantizer based on code information for the bit.
15. The method of claim 14 , wherein the code information includes a number of unsatisfied checks connected to the bit and degree of the bit.
16. The method of claim 11 , further comprising:
training the deep learning model on failed bits.
17. The method of claim 16 , wherein the deep learning model is based on a function that minimizes cross-entropy between a genie LLR for the bit and an output of the function.
18. The method of claim 11 , further comprising:
performing hard decoding of the codeword before performing the first soft decoding.
19. The method of claim 11 , wherein each of the first, second and third soft decoding comprises low-density parity-check (LDPC) soft decoding.