Passive dynamic biasing for MOSFET cascode
A driver circuit has a plurality of transistors in a cascode arrangement. A passive biasing circuit is coupled to a gate terminal of a first transistor of the plurality of transistors. The passive biasing circuit has a first resistor coupled to a circuit node to provide a first biasing signal, a first capacitor coupled between the circuit node and a power supply conductor, a second resistor coupled between the circuit node and a drain terminal of the first transistor, and a third resistor coupled between the circuit node and a source terminal of the first transistor. A second transistor has a gate terminal coupled for receiving a data signal which controls an optical device.
1. A driver circuit, comprising:
a plurality of transistors of a same conductivity type coupled in a cascode arrangement; and
a first passive biasing circuit coupled to a gate terminal of a first transistor of the plurality of transistors, the first passive biasing circuit including,
(a) a biasing circuit coupled to a circuit node to provide a first biasing signal to the gate terminal of the first transistor,
(b) a first capacitor coupled between the circuit node and a power supply conductor,
(c) a first resistor coupled between the circuit node and a drain terminal of the first transistor, and
(d) a second resistor coupled between the circuit node and a source terminal of the first transistor.
2. The driver circuit of claim 1 , further including:
a second passive biasing cell providing a second biasing signal; and
a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving the second biasing signal.
3. The driver circuit of claim 1 , further including a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving a data signal.
4. The driver circuit of claim 1 , further including a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving a second biasing signal.
5. The driver circuit of claim 1 , wherein the biasing circuit includes:
a voltage source; and
a third resistor coupled between the voltage source and the circuit node.
6. A driver circuit, comprising:
a plurality of transistors in a cascode arrangement; and
a first passive biasing circuit coupled to a gate terminal of a first transistor of the plurality of transistors, the first passive biasing circuit including,
(a) a biasing circuit coupled to a circuit node to provide a first biasing signal to the gate terminal of the first transistor,
(b) a first capacitor coupled between the circuit node and a power supply conductor,
(c) a first resistor coupled between the circuit node and a drain terminal of the first transistor, and
(d) a second resistor coupled between the circuit node and a source terminal of the first transistor,
wherein the biasing circuit includes:
a current source coupled to the circuit node, and
a third resistor coupled in parallel with the current source.
7. A driver circuit, comprising:
a first metal oxide semiconductor (MOS) transistor; and
a first passive biasing circuit coupled to a gate terminal of a first MOS transistor, the first passive biasing circuit including,
(a) a biasing circuit coupled to a circuit node to provide a first biasing signal to the gate terminal of the first MOS transistor, wherein the biasing circuit includes a current source coupled to the circuit node, and a third resistor coupled in parallel with the current source,
(b) a first capacitor coupled between the circuit node and a power supply conductor,
(c) a first resistor coupled between the circuit node and a drain terminal of the first MOS transistor, and
(d) a second resistor coupled between the circuit node and a source terminal of the first MOS transistor.
8. The driver circuit of claim 7 , further including:
a second MOS transistor of a same conductivity type as the first transistor and coupled in a cascode arrangement with the first MOS transistor; and
a second passive biasing circuit providing a second biasing signal to a gate terminal of the second MOS transistor.
9. The driver circuit of claim 7 , wherein the biasing circuit further includes:
a voltage source; and
a third resistor coupled between the voltage source and the circuit node.
10. The driver circuit of claim 7 , further including a second MOS transistor in a cascode arrangement with the first MOS transistor and including a gate terminal coupled for receiving a data signal.
11. A method of making a driver circuit, comprising:
providing a plurality of transistors of a same conductivity type coupled in a cascode arrangement; and
providing a first passive biasing circuit coupled to a gate terminal of a first transistor of the plurality of transistors, the first passive biasing circuit including,
(a) a biasing circuit coupled to a circuit node to provide a first biasing signal to the gate terminal of the first transistor,
(b) a first capacitor coupled between the circuit node and a power supply conductor,
(c) a first resistor coupled between the circuit node and a drain terminal of the first transistor, and
(d) a second resistor coupled between the circuit node and a source terminal of the first transistor.
12. The method of claim 11 , further including:
providing a second passive biasing cell for producing a second biasing signal; and
providing a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving the second biasing signal.
13. The method of claim 11 , wherein the biasing circuit includes:
a voltage source; and
a third resistor coupled between the voltage source and the circuit node.
14. The method of claim 11 , wherein the biasing circuit includes:
a current source coupled to the circuit node; and
a third resistor coupled in parallel with the current source.
15. The method of claim 11 , further including a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving a data signal.
16. The method of claim 11 , further including a second transistor of the plurality of transistors comprising a gate terminal coupled for receiving a second biasing signal.
17. The method of claim 11 , further including providing a laser diode coupled to an output of the driver circuit.