Single-chip control module for an integrated system-on-a-chip for silicon photonics

1. A communication network system, the system comprising:

a communication network comprising a communication interface;

a communication apparatus coupled to the network using the communication interface, the apparatus comprising:

an integrated single-chip device for a system-on-a-chip in the communication network, the integrated single-chip device comprising:

a silicon substrate member;

a data input/output interface provided on the silicon substrate member and configured for a predefined data rate and protocol;

an input/output block provided on the silicon substrate member and coupled to the data input/output interface, the input/output block comprising a receiving block and a transmitting block for respectively receiving and transmitting data signal with a first rate from and to a very-short-reach (VSR) network host;

a signal processing block provided on the silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol;

a driver module provided on the silicon substrate member and coupled to the signal processing block using a uni-directional multi-lane bus;

a driver interface provided on the silicon substrate member and coupled to the driver module and configured to couple to a silicon photonics device, the driver interface being configured to transmit output data in an amplitude modulation format with a second data rate equal to 2× of the first data rate;

a receiver module provided on the silicon substrate member and configured to couple to the silicon photonics device using predefined modulation format to receive information converted from optical signals and couple to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface;

a communication block provided on the silicon substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module for multiple series communications.

2. The system of claim 1 wherein the driver module is selected from a current drive or a voltage driver.

3. The system of claim 1 wherein the driver module is a differential driver.

4. The system of claim 1 wherein the amplitude modulation format is selected from NRZ format or PAM-4 format.

5. The system of claim 1 wherein the data input/output interface is configured to receive/send electrical signals from/to the VSR host up to eight channels with the first data rate of 50 Gbps in PAM-4 format.

6. The system of claim 1 wherein the driver interface is configured to transmit output data up to 4 channels with the second data rate of 100 Gbps in PAM-4 format.

7. The system of claim 1 wherein the driver module and the receiver module comprise a Backplane Ethernet KR physical link for coupling with the silicon photonics device.

8. The system of claim 1 wherein the silicon photonic device is configured to convert the output data into an output transport data in a WDM optical signal with an amplitude modulation format.

9. The system of claim 1 wherein the driver module is configured to couple with a control block for initiating control of a laser bias or a modulator bias for the silicon photonics device.

10. The system of claim 9 wherein the control block is configured to drive a thermal tuning or carrier tuning device each of which is configured on the silicon photonics device.

11. The system of claim 1 wherein the receiver module is configured to convert optical signals from the silicon photonics device to electrical current signals.

12. The system of claim 1 wherein the signal processing block comprises a first digital logic block including a cross-point switch coupled to the receiving block and the driver module, and a second digital logic block including a cross-point switch coupled to the transmitting block and the receiver module.

13. The system of claim 12 wherein the signal processing block is characterized by high performance in >30 dB DFE/FFE/CLTE optimized equalization for both signal transmission and receiving.

14. The system of claim 1 wherein the first digital logic block and the second digital logic block comprise a SerDes block configured to convert data streams of N into data streams of M and a forward error correction (FEC) block configured to supporting signal transmission over 10 km distance.

15. The system of claim 1 wherein the communication block comprises a multi-point control unit (MCU) and a phase-locked loop (PLL) with a reference clock input.

16. The system of claim 1 wherein the communication interface comprises a Management Data Input/Output interface or an I2C-type interface.

17. The system of claim 15 wherein the communication block further comprises a test/diagnostics unit including a general purpose Input/Output port for communicating host and line loopbacks, a Scan port for supporting Eye-Scan/Histograms, and a test access port with JTAG interface.

18. The system of claim 15 wherein the communication block further comprises a power supply module configured to receive power supplies of 0.65 V and 1.1 V.