Dynamic element matching
A system includes an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit includes a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.
1. A system comprising:
an input shuffling circuit comprising a data input, a data output, a mode select input, and a shuffle control input wherein the input shuffling circuit is operable to:
receive, via the data input, an N-bit binary value, wherein N is an integer; and
route each of the N bits of the N-bit binary value to one or more of M bits of the data output to generate an M-bit value, wherein M=2 N , and the route is based on a control value applied to the mode select input; and
digital-to-analog conversion circuitry operable to convert the M-bit value to a corresponding analog voltage and/or current.
2. The system of claim 1 , wherein M different values applied to the shuffle control input result in M different routings of the N bits of the binary value.
3. The system of claim 1 , wherein the input shuffling circuit comprises a plurality of multiplexers.
4. The system of claim 1 , wherein the input shuffling circuit comprises a two-to-two multiplexer, a four-to-four multiplexer, and an eight-to-eight multiplexer.
5. The system of claim 4 , wherein:
two outputs of the two-to-two multiplexer are connected to two of four data inputs of the four-to-four multiplexer; and
four outputs of the four-to-four multiplexer are connected to four of eight data inputs of the eight-to-eight multiplexer.
6. The system of claim 5 , wherein:
one bit of the N-bit value is connected to one of two data inputs of the two-to-two multiplexer;
one bit of the N-bit value is connected to two of four data inputs of the four-to-four multiplexer; and
one bit of the N-bit value is connected to four of eight data inputs of the eight-to-eight multiplexer.
7. The system of claim 1 , wherein the route is based on a value applied to the shuffle select input.
8. The system of claim 1 , wherein:
a first value applied to the mode select input configures the input shuffling circuit into a dynamic element matching mode; and
a second value applied to the mode select input configures the input shuffling circuit into a binary-to-thermometer conversion mode.
9. The system of claim 1 , wherein:
a first value applied to the mode select input configures the input shuffling circuit into a dynamic element matching mode; and
a second value applied to the mode select input configures the input shuffling circuit into a binary-to-thermometer conversion mode.
10. A method comprising:
in a system comprising digital-to-analog conversion circuitry and an input shuffling circuit comprising a data input, a data output, mode select input, and a shuffle control input:
receiving, by the input shuffling circuit via the data input, an N-bit binary value, where N is an integer;
generating, by the input shuffling circuit, an M-bit value by routing each of the N bits of the N-bit binary value to one or more of M bits of the data output, where M=2 N , and the routing is based on a value applied to the mode select input; and
converting, by the digital-to-analog conversion circuitry, the M-bit value to
a corresponding analog voltage and/or current.
11. The method of claim 10 , wherein M different values applied to the shuffle control input result in M different routings of the N bits of the binary value.
12. The method of claim 10 , wherein the input shuffling circuit comprises a plurality of multiplexers.
13. The method of claim 10 , wherein the input shuffling circuit comprises a two-to-two multiplexer, a four-to-four multiplexer, and an eight-to-eight multiplexer.
14. The method of claim 13 , wherein:
two outputs of the two-to-two multiplexer are connected to two of four data inputs of the four-to-four multiplexer; and
four outputs of the four-to-four multiplexer are connected to four of eight data inputs of the eight-to-eight multiplexer.
15. The method of claim 14 , wherein:
one bit of the N-bit value is connected to one of two data inputs of the two-to-two multiplexer;
one bit of the N-bit value is connected to two of four data inputs of the four-to-four multiplexer; and
one bit of the N-bit value is connected to four of eight data inputs of the eight-to-eight multiplexer.
16. The method of claim 10 , wherein the route is based on a value applied to the shuffle control input.
17. The method of claim 10 , comprising:
selecting a dynamic element matching mode when a first value is applied to the mode select input; and
selecting a binary-to-thermometer conversion mode when a second value is applied to the mode select input.
18. The method of claim 10 , comprising:
configuring the input shuffling circuit into a dynamic element matching mode when a first value is applied to the mode select input; and
configuring the input shuffling circuit into a binary-to-thermometer conversion mode when a second value is applied to the mode select input.
19. The method of claim 10 , comprising varying, over time, a value applied to the shuffle control input.
20. The method of claim 19 , wherein the value applied to the shuffle control input is a pseudo-random N-bit value that varies at an input rate of the N-bit binary value.