IP Library Granted Patent US 10,930,796
Granted Patent B2
US 10,930,796 · App. 16/406,228 · Granted Feb 23, 2021

Merged p-intrinsic-N (PIN) Schottky diode

Inventors: Wonhwa Lee (Bucheon-si, KR); Kwangwon Lee (Incheon, KR); Jaegil Lee (Incheon, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/868H01L29/0619H01L29/08H01L29/417H01L29/66143H01L29/872H01L29/0634H01L29/0657
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Quick Facts
Patent No.
US 10,930,796
App. No.
16/406,228
Granted
Feb 23, 2021
Kind
B2
Abstract

In a general aspect, a method can include forming a first pillar of a first conductivity type and a second pillar of a second conductivity type, alternately disposed with the first pillar. The second pillar can be in direct contact with the first pillar. The method can also include forming an implant of the second conductivity type in an upper portion of the second pillar. The implant can have a doping concentration that is higher than a doping concentration of a lower portion of the second pillar. The method can further include forming a Schottky metal layer having a first portion directly disposed on an upper surface of the first pillar and a second portion directly disposed on the implant along an upper surface of the second pillar. The first portion of the Schottky metal layer can be wider than the second portion of the Schottky metal layer.

Claims (59)

1. A method comprising:

forming, in a semiconductor substrate:

a first pillar of a first conductivity type; and

a second pillar of a second conductivity type, the first pillar and the second pillar being alternately disposed, the second pillar being in direct contact with the first pillar;

forming an implant of the second conductivity type in an upper portion of the second pillar, the implant having a doping concentration that is higher than a doping concentration of a lower portion of the second pillar;

forming a textured pattern on an upper surface of the first pillar; and

forming a Schottky metal layer having:

a first portion directly and conformally disposed on the textured pattern on the upper surface of the first pillar; and

a second portion directly disposed on the implant along an upper surface of the second pillar,

the first portion of the Schottky metal layer being wider than the second portion of the Schottky metal layer.

2. The method of claim 1 , wherein forming the Schottky metal layer includes forming a third portion of the Schottky metal layer that is disposed between the first portion of the Schottky metal layer and the second portion of the Schottky metal layer, the third portion of the Schottky metal layer being in contact with the first pillar and the second pillar.

3. A method comprising:

forming, in a semiconductor region of a first conductivity type, a charge balance structure, the forming the charge balance structure including:

forming a trench disposed in the semiconductor region, the trench defining a mesa of the semiconductor region on a side of the trench;

disposing a semiconductor material of a second conductivity type in the trench, the semiconductor material being recessed in the trench, so as to define a recess, the recess having a sidewall and a bottom surface, the semiconductor material of the second conductivity type being in direct contact with the semiconductor region;

forming an implant of the second conductivity type disposed in an upper portion of the semiconductor material along the bottom surface of the recess and along at least a lower portion of the sidewall of the recess, the implant having a doping concentration that is higher than a doping concentration of the semiconductor material of the second conductivity type; and

forming a metal layer that is:

directly disposed on an upper surface of the mesa;

directly disposed on the implant along the sidewall of the recess, and

directly disposed on the implant along the bottom surface of the recess.

4. The method of claim 3 , wherein forming the metal layer includes defining a Schottky interface:

between the upper surface of the mesa and the metal layer; and

between an upper portion of the sidewall of the recess and the metal layer.

5. The method of claim 3 , wherein forming the metal layer includes defining an Ohmic contact:

between the lower portion of the sidewall of the recess and the metal layer; and

between the bottom surface of the recess and the metal layer.

6. The method of claim 3 , wherein the trench has a depth in the semiconductor region in a range of 50-100 microns (μm) and the recess has a depth in the semiconductor region in a range of 5-15 μm.

7. The method of claim 3 , wherein the mesa is a first mesa, the side of the trench is a first side, the sidewall is a first sidewall, the trench defines a second mesa of the semiconductor region on a second side of the trench, the recess has a second sidewall, and the metal layer is further disposed on the second sidewall and the second mesa,

the forming the metal layer further including defining a Schottky interface between:

at least an upper portion of the second sidewall and the metal layer; and

the second mesa and the metal layer.

8. The method of claim 3 , wherein the sidewall of the recess is substantially orthogonal with respect to the bottom surface of the recess.

9. The method of claim 3 , wherein the sidewall of the recess and the bottom surface of the recess define an angle, the angle being greater than 90 degrees.

10. The method of claim 3 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

11. The method of claim 3 , wherein the implant is a boron implant.

12. The method of claim 3 , wherein the semiconductor region is disposed on a semiconductor substrate of a first conductivity type,

the semiconductor substrate having a doping concentration between 1.0×10 14 atoms/cm 3 and 1.0×10 17 atoms/cm 3 ;

the semiconductor material of the second conductivity type having a doping concentration between 1.0×10 14 atoms/cm 3 and 1.0×10 17 atoms/cm 3 ; and

the implant having a doping concentration between 2.0×10 17 atoms/cm 3 and 1.0×10 20 atoms/cm 3 .

13. A method comprising:

forming, in a semiconductor region of a first conductivity type, a charge balance structure, the forming the charge balance structure including:

forming a trench, the trench defining a mesa of the semiconductor region on a side of the trench;

disposing a semiconductor material of a second conductivity type in the trench, the semiconductor material being in direct contact with the semiconductor region, the semiconductor material being recessed in the trench, so as to define a recess above the semiconductor material in the trench, the recess having a sidewall and a bottom surface, the sidewall being defined by the mesa;

forming an implant of the second conductivity type between the bottom surface of the recess and above a top surface of the semiconductor material, the implant having a doping concentration that is higher than a doping concentration of the semiconductor material; and

forming a Schottky metal layer:

directly on an upper surface of the mesa;

directly on the implant along the sidewall of the recess; and

directly on the implant along the bottom surface of the recess.

14. The method of claim 13 , wherein the forming the Schottky metal layer includes defining a Schottky interface between:

the upper surface of the mesa and the Schottky metal layer; and

at least an upper portion of the sidewall of the recess and the Schottky metal layer.

15. The method of claim 14 , wherein the forming the Schottky metal layer includes defining an Ohmic contact with:

a lower portion of the sidewall of the recess; and

the bottom surface of the recess.

16. The method of claim 13 , wherein a portion of the implant is disposed along at least a lower portion of the sidewall of the recess.

17. The method of claim 13 , further comprising forming a metal electrode layer on:

the Schottky metal layer on the upper surface of the mesa;

on the Schottky metal layer on the sidewall of the recess; and

on the Schottky metal layer on the bottom surface of the recess.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 050156, FRAME 0421 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0639 →
SECURITY INTEREST Recorded Aug 23, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 050156/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2019
From: LEE, WONHWA; LEE, KWANGWON; LEE, JAEGIL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049112/0542 →