IP Library Granted Patent US 11,258,352
Granted Patent B2
US 11,258,352 · App. 16/409,516 · Granted Feb 22, 2022

Systems and methods for fast response and low total harmonic distortion power factor correction

Inventors: Constantin Darius Livescu (Austin, TX); Mark A. Muccini (Georgetown, TX)
Assignee: Dell Products L.P.
H02M1/4208G06F1/28H02M1/12H02M1/0009
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Quick Facts
Patent No.
US 11,258,352
App. No.
16/409,516
Granted
Feb 22, 2022
Kind
B2
Abstract

A system may include a power train comprising a rectifier and power factor correction stage configured to receive an alternating current (AC) input voltage waveform and convert the AC input voltage waveform into a regulated direct current (DC) voltage on a bulk capacitor configured to store electrical charge and a controller configured to control the rectifier and power factor correction stage to perform power factor correction between the AC input voltage waveform and an AC input current waveform related to the AC input voltage waveform. The controller may implement a voltage regulation loop configured to regulate the regulated DC voltage on the bulk capacitor to a desired constant average value based on a combination of a DC current signal associated with the power train and a voltage loop error signal based on the regulated DC voltage and a current loop regulating the shape of the AC input current waveform to a sinusoidal value in phase with the AC input voltage waveform.

Claims (28)

1. A system comprising:

a power train comprising a rectifier and power factor correction stage configured to receive an alternating current (AC) input voltage waveform and convert the AC input voltage waveform into a regulated direct current (DC) voltage on a bulk capacitor configured to store electrical charge; and

a controller configured to control the rectifier and power factor correction stage to perform power factor correction between the AC input voltage waveform and an AC input current waveform related to the AC input voltage waveform by implementing:

a voltage regulation loop configured to regulate the regulated DC voltage on the bulk capacitor to a desired constant average value based on a combination of a DC current signal associated with the power train and a voltage loop error signal based on the regulated DC voltage; and

a current loop regulating the shape of the AC input current waveform to a sinusoidal value in phase with the AC input voltage waveform.

2. The system of claim 1 , wherein the voltage loop error signal is indicative of a difference between the regulated DC voltage and the desired constant average value.

3. The system of claim 1 , wherein the DC current signal is proportional to an output current generated by the rectifier and power factor correction stage.

4. The system of claim 1 , wherein the power train further comprises a direct current-to-direct current (DC/DC) converter stage configured to convert the regulated DC voltage into a second regulated DC voltage.

5. The system of claim 4 , wherein the DC current signal is proportional to an output current generated by the DC/DC converter stage.

6. An information handling system comprising:

at least one information handling resource; and

a power supply unit for supplying electrical energy to the at least one information handling resource, the power supply unit comprising:

a power train comprising a rectifier and power factor correction stage configured to receive an alternating current (AC) input voltage waveform and convert the AC input voltage waveform into a regulated direct current (DC) voltage on a bulk capacitor configured to store electrical charge; and

a controller configured to control the rectifier and power factor correction stage to perform power factor correction between the AC input voltage waveform and an AC input current waveform related to the AC input voltage waveform by implementing:

a voltage regulation loop configured to regulate the regulated DC voltage on the bulk capacitor to a desired constant average value based on a combination of a DC current signal associated with the power train and a voltage loop error signal based on the regulated DC voltage; and

a current loop regulating the shape of the AC input current waveform to a sinusoidal value in phase with the AC input voltage waveform.

7. The information handling system of claim 6 , wherein the voltage loop error signal is indicative of a difference between the regulated DC voltage and the desired constant average value.

8. The information handling system of claim 6 , wherein the DC current signal is proportional to an output current generated by the rectifier and power factor correction stage.

9. The information handling system of claim 6 , wherein the power train further comprises a direct current-to-direct current (DC/DC) converter stage configured to convert the regulated DC voltage into a second regulated DC voltage.

10. The information handling system of claim 9 , wherein the DC current signal is proportional to an output current generated by the DC/DC converter stage.

11. A method comprising, in a power train comprising a rectifier and power factor correction stage configured to receive an alternating current (AC) input voltage waveform and convert the AC input voltage waveform into a regulated direct current (DC) voltage on a bulk capacitor configured to store electrical charge:

controlling the rectifier and power factor correction stage to perform power factor correction between the AC input voltage waveform and an AC input current waveform related to the AC input voltage waveform by implementing:

a voltage regulation loop configured to regulate the regulated DC voltage on the bulk capacitor to a desired constant average value based on a combination of a DC current signal associated with the power train and a voltage loop error signal based on the regulated DC voltage; and

a current loop regulating the shape of the AC input current waveform to a sinusoidal value in phase with the AC input voltage waveform.

12. The method of claim 11 , wherein the voltage loop error signal is indicative of a difference between the regulated DC voltage and the desired constant average value.

13. The method of claim 11 , wherein the DC current signal is proportional to an output current generated by the rectifier and power factor correction stage.

14. The method of claim 11 , wherein the power train further comprises a direct current-to-direct current (DC/DC) converter stage configured to convert the regulated DC voltage into a second regulated DC voltage.

15. The method of claim 14 , wherein the DC current signal is proportional to an output current generated by the DC/DC converter stage.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (050724/0571) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0088 →
RELEASE OF SECURITY INTEREST AT REEL 050406 FRAME 421 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058213/0825 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 15, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 050724/0571 →
SECURITY AGREEMENT Recorded Sep 17, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 050406/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2019
From: LIVESCU, CONSTANTIN DARIUS; MUCCINI, MARK A.
To: DELL PRODUCTS L.P.
Reel/Frame 049145/0522 →