Method for injecting deliberate errors into PCIE device for test purposes, apparatus applying method, and computer readable storage medium for code of method
View Patent ↗A method for injecting specific errors of both correctable and non-correctable types into a PCIE device for testing purposes during fabrication stage constructs an error injecting platform based on received target information. The platform includes a control system and at least one testing system. Disabling a security boot in the connected testing system and obtaining information of the specified driver. The obtained information comprises objects to be tested according to selection, each object having a bus address and a PCIE port value. The object under test is controlled to inject a specified error, the injection and result of injection being reported by the processor and analyzed.
1. A PCIE error injecting method comprising:
constructing a platform for injecting errors based on received target information; the platform comprises a control system and at least one testing system;
disabling a security boot of the connected testing system in response to a setting command;
obtaining specified bus information of a specified driver; the specified bus information comprises a plurality of objects; each object comprises a bus address and a port value;
selecting a specified object to be tested based on the specified bus information in response to a selecting command;
controlling the specified object to inject at least one specified error in response to an error injecting selecting command; and
obtaining a result of the injection by a processor and analyzing;
wherein the specified error is a non-correctable error type.
2. The PCIE error injecting method of claim 1 , wherein there are a correctable error type and a non-correctable error type; and each error type corresponds to multiple errors; the correctable error type corresponds to a first type code, and the non-correctable error type corresponds to a second type code; each error corresponds to an identified value; the step of controlling the specified object to inject at least one specified error in response to an error injecting selecting command comprising:
obtaining a type code;
determining whether the obtained type code is the first type code;
when the obtained type code is the first type code, displaying the correctable errors corresponding to the correctable error type;
when the obtained type code is the second type code, displaying the non-correctable errors corresponding to the non-correctable error type;
obtaining a specified error by inputting the corresponding identified value; and
injecting the specified error.
3. The PCIE error injecting method of claim 1 , wherein before the step of obtaining specified bus information of the specified driver, the PCIE error injecting method further comprising:
determining whether a specified driver is installed in response to a determining command; and
when no specified driver is installed, automatically executing an installation of the specified driver.
4. The PCIE error injecting method of claim 1 , wherein the target information comprises a testing system information and a controlling system information; the testing system information comprises an IP address, a user name, and a password; the controlling system information comprises a BMC IP address, a user name, and a password.
5. The PCIE error injecting method of claim 1 , wherein the PCIE error injecting method further comprising:
forming a report file in a specified format in response to an exporting command.
6. The PCIE error injecting method of claim 5 , wherein the analyzing operation is executed by searching a record in a specified storage device for determining success or non-success of the error injection.
7. A PCIE error injecting apparatus comprising:
a processor; and
a storage medium storing one or more programs, which, when executed by the processor, cause the processor to:
construct an error injecting platform based on received target information; the error injecting platform comprises a control system and at least one testing system;
set a security boot in a disable state of the connected testing system in response to a setting command;
obtain specified bus information of the specified driver;
the specified bus information comprises a plurality of objects; each object comprises a bus address and a port value;
select a specified object to be tested a based on the specified bus information in response to a selecting command;
control the specified object to inject at least one specified error in response to an error injecting selecting command; and
obtain a result of the injecting processor and analyze;
wherein the specified error is a non-correctable error type.
8. The PCIE error injecting apparatus of claim 7 , wherein there are a correctable error type and a non-correctable error type; and each error type corresponds to multiple errors; the correctable error type corresponds to a first type code, and the non-correctable error type corresponds to a second type code; each error corresponds to an identified value; the processor obtains a type code and determines whether the obtained type code is the first type code; when the obtained type code is the first type code, the processor displays the correctable errors corresponding to the correctable error type; when the obtained type code is the second type code, the processor displays the non-correctable errors corresponding to the non-correctable error type; the processor obtains a specified error by inputting the corresponding identified value; the processor injects the specified error.
9. The PCIE error injecting apparatus of claim 7 , wherein the processor determines whether a specified driver is installed in response to a determining command; when no specified driver is installed, the processor automatically executing an installation of the specified driver.
10. The PCIE error injecting apparatus of claim 7 , wherein the target information comprises a testing system information and a controlling system information; the testing system information comprises an IP address, a user name, and a password; the controlling system information comprises a BMC IP address, a user name, and a password.
11. The PCIE error injecting apparatus of claim 7 , wherein the processor forms a report file in a specified format in response to an exporting command.
12. The PCIE error injecting apparatus of claim 11 , wherein the analyzing operation is executed by searching a record in a specified storage device for determining success or non-success of the error injection.
13. A non-transitory computer readable storage medium, wherein the computer readable storage medium stores a system for injecting PCIE errors, when being executed by at least one processor, the system performs the following steps:
constructing a platform for injecting errors based on received target information; the platform comprises a control system and at least one testing system;
disabling a security boot of the connected testing system in response to a setting command;
obtaining specified bus information of a specified driver; the specified bus information comprises a plurality of objects; each object comprises a bus address and a port value;
selecting a specified object to be tested based on the specified bus information in response to a selecting command;
controlling the specified object to inject at least one specified error in response to an error injecting selecting command; and
obtaining a result of the injection by a processor and analyzing;
wherein the specified error is a non-correctable error type.
14. The non-transitory computer readable storage medium of claim 13 , wherein there are a correctable error type and a non-correctable error type; and each error type corresponds to multiple errors; the correctable error type corresponds to a first type code, and the non-correctable error type corresponds to a second type code; each error corresponds to an identified value; the step of controlling the specified object to inject at least one specified error in response to an error injecting selecting command comprising:
obtaining a type code;
determining whether the obtained type code is the first type code;
when the obtained type code is the first type code, displaying the correctable errors corresponding to the correctable error type;
when the obtained type code is the second type code, displaying the non-correctable errors corresponding to the non-correctable error type;
obtaining a specified error by inputting the corresponding identified value; and
injecting the specified error.
15. The non-transitory computer readable storage medium of claim 13 , wherein before the step of obtaining specified bus information of the specified driver, the PCIE error injecting method further comprising:
determining whether a specified driver is installed in response to a determining command; and
when no specified driver is installed, automatically executing an installation of the specified driver.
16. The non-transitory computer readable storage medium of claim 13 , wherein the target information comprises a testing system information and a controlling system information; the testing system information comprises an IP address, a user name, and a password; the controlling system information comprises a BMC IP address, a user name, and a password.
17. The non-transitory computer readable storage medium of claim 16 , wherein the analyzing operation is executed by searching a record in a specified storage device for determining success or non-success of the error injection.
18. The non-transitory computer readable storage medium of claim 13 , wherein the PCIE error injecting method further comprising:
forming a report file in a specified format in response to an exporting command.