IP Library Granted Patent US 11,112,303
Granted Patent B2
US 11,112,303 · App. 16/410,320 · Granted Sep 7, 2021

Measurement circuit and method therefor

Inventors: Dieter Jozef Joos (Nieuwenrode, BE); Thomas Sevrin (Jemeppe-sur-Sambre, BE); Patrick Lepers (Céroux-Mousty, BE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G01J1/44H03F3/45071H03F2200/129H03F2203/45116H03F2203/45526
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Quick Facts
Patent No.
US 11,112,303
App. No.
16/410,320
Granted
Sep 7, 2021
Kind
B2
Abstract

In embodiment, a measurement circuit forms a compensation signal that is representative of disturbances that are received while the measurement circuit is not receiving a signal to be measured, then the circuit removes the compensation signal from the measurement signal before measuring the value of the measurement signal.

Claims (33)

1. A measurement circuit comprising:

a measurement channel circuit configured to receive an input signal from an input of the measurement circuit and measure a value of the input signal;

a regulation circuit having a first switch configured to selectively couple the regulation circuit to regulate the input to a first value during a first time interval and to selectively decouple the regulation circuit from regulating the input during a second time interval wherein the measurement circuit receives a measurement signal at the input within the second time interval but not during the first time interval;

a sampling circuit having a variable impedance circuit configured to selectively couple the sampling circuit to receive the input signal and to selectively increase an impedance of the variable impedance circuit to form a compensation signal that is representative of the input signal wherein the sampling circuit forms the compensation signal while the regulation circuit is regulating the input to the first value and wherein the sampling circuit is decoupled from receiving the input signal in response to the regulation circuit being decoupled from regulating the input; and

the sampling circuit configured to selectively apply the compensation signal to the input for at least a portion of the second time interval wherein the measurement circuit receives the measurement signal to be measured at the input for the portion of the second time interval.

2. The measurement circuit of claim 1 wherein the regulation circuit includes an amplifier coupled to receive the input signal and form an output signal on an output of the amplifier wherein the first switch is configured to couple the output of the amplifier to the input.

3. The measurement circuit of claim 1 wherein the sampling circuit stores a signal from the variable impedance circuit on a first capacitor to form the compensation signal.

4. The measurement circuit of claim 1 wherein the variable impedance circuit is configured to increase the impedance by increasing a resistance of the variable impedance circuit over a plurality of periods of the input signal.

5. The measurement circuit of claim 4 wherein the variable impedance circuit is an MOS transistor configured to increase an on-resistance of the MOS transistor over the plurality of periods of the input signal.

6. The measurement circuit of claim 4 wherein the variable impedance circuit increases the resistance over at least five periods of the input signal.

7. The measurement circuit of claim 4 wherein the variable impedance circuit increases the resistance over a time of between approximately five microseconds to approximately ten microseconds.

8. The measurement circuit of claim 1 wherein the sampling circuit is configured to form the compensation signal during a latter portion of the first time interval and to apply the compensation signal to the input during a latter portion of the second time interval.

9. The measurement circuit of claim 8 wherein the sampling circuit is configured to store the input signal on a first capacitor as the compensation signal during the latter portion of the first time interval and to selectively transfer the compensation signal from the first capacitor to a second capacitor during an early portion of the second time interval wherein the early portion of the second time interval occurs prior to the latter portion of the second time interval.

10. The measurement circuit of claim 8 wherein the measurement circuit applies the measurement signal to the input during the latter portion of the second time interval.

11. A measurement circuit comprising:

a measurement channel circuit configured to receive an input signal from an input of the measurement circuit and measure a value of the input signal;

a regulation circuit configured to regulate the input to a first value during a first time interval and to selectively not regulate the input to the first value during a second time interval;

a sampling circuit configured to form substantially an average value of the input signal over a plurality of cycles of the input signal wherein the sampling circuit forms substantially the average value over at least a portion of the first time interval while the regulation circuit is regulating the input to the first value; and

an output circuit of the sampling circuit configured to apply a first signal that is representative of substantially the average value to the input during a portion of the second time interval, the output circuit configured to decouple the input from receiving the first signal during the first time interval.

12. The measurement circuit of claim 11 wherein the sampling circuit terminates forming the average value in response to the second time interval.

13. The measurement circuit of claim 11 wherein the input signal received on the input is a signal from a photo-diode that receives ambient light during the first time interval and receives light from an LED during the portion of the second time interval.

14. The measurement circuit of claim 11 wherein the sampling circuit includes a variable impedance circuit that receives the input signal and varies an impedance of the variable impedance circuit over the portion of the first time interval to reduce a cut-off frequency of a filter.

15. The measurement circuit of claim 14 wherein the variable impedance circuit is configured to increase an on-resistance of an MOS transistor over the portion of the first time interval.

16. The measurement circuit of claim 14 wherein the sampling circuit includes a capacitor coupled to the variable impedance circuit to store an output of the variable impedance circuit as the average value.

17. The measurement circuit of claim 11 wherein the sampling circuit is configured to store the substantially average value on a first capacitor during the portion of the first time interval and configured to transfer substantially the average value to a second capacitor during the second time interval and prior to the portion of the second time interval.

18. A method of forming a compensation circuit comprising:

configuring the compensation circuit to receive, from an input, a first signal to be measured;

configuring the compensation circuit to regulate the input to a first value for a first time interval while not receiving the first signal and to receive an input signal for the first time interval;

configuring the compensation circuit to filter the input signal to form a sample signal in response to decreasing a cut-off frequency of a filter circuit from a first cut-off frequency to a second cut-off frequency over a portion of the first time interval; and

configuring the compensation circuit to cease regulating the input to the first value and to apply a signal that is representative of the sample signal to the input for a second time interval wherein during at least a portion of the second time interval the compensation circuit is not regulating the input to the first value and the first signal is formed at the input thereby removing the sample signal from the first signal to form a compensated first signal.

19. The method of claim 18 wherein configuring the compensation circuit to receive, from the input, includes configuring the compensation circuit to receive the first signal from the input of the compensation circuit; and

configuring a measurement channel circuit to measure the compensated first signal.

20. The method of claim 18 including configuring the compensation circuit to decrease the cut-off frequency to form the sample signal as an average value of the input signal.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 050156, FRAME 0421 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0639 →
SECURITY INTEREST Recorded Aug 23, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 050156/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2019
From: JOOS, DIETER JOZEF; SEVRIN, THOMAS; LEPERS, PATRICK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049159/0596 →