Semiconductor package structure
A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.
1. A semiconductor package structure, comprising:
a first semiconductor die having an active surface and a passive surface opposite to the active surface;
a conductive element leveled with the first semiconductor die;
a first redistribution layer (RDL) being closer to the passive surface than to the active surface;
a second RDL being closer to the active surface than to the passive surface; and
a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL,
wherein a first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die, and
wherein the second semiconductor die electrically coupled to the first semiconductor die through a high bump density region of the second semiconductor die.
2. The semiconductor package structure of claim 1 , wherein the second semiconductor die further electrically coupled to the first RDL through a low bump density region of the second semiconductor die.
3. The semiconductor package structure of claim 1 , wherein a conductive pattern of the high bump density region of the second semiconductor die substantially matches a conductive pattern of a high bump density region of the first semiconductor die at the active surface.
4. The semiconductor package structure of claim 1 , wherein the second semiconductor die comprises a waveguide layer.
5. The semiconductor package structure of claim 1 , wherein the passive surface of the first semiconductor die is aligned with a bottom surface of the conductive element.
6. The semiconductor package structure of claim 1 , further comprising:
a substrate at a side of the passive surface of the first semiconductor die; and
a first conductive terminal connecting the substrate and the first RDL,
wherein the conductive path further includes the first conductive terminal.
7. The semiconductor package structure of claim 6 , further comprising a second conductive terminal under a projected area of the first semiconductor die and connected to the first RDL.
8. The semiconductor package structure of claim 7 , wherein the second conductive terminal is electrically coupled to a ground line or a floating line of the substrate.
9. The semiconductor package structure of claim 8 , wherein the first conductive terminal is electrically coupled to a signal line of the substrate.
10. A semiconductor package structure, comprising:
a first semiconductor die having an active surface and a passive surface opposite to the active surface;
a conductive element leveled with the first semiconductor die;
a first redistribution layer (RDL) being closer to the passive surface than to the active surface;
a second RDL being closer to the active surface than to the passive surface; and
a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL,
wherein the second semiconductor die comprises a waveguide layer, and
wherein an active surface of the second semiconductor die comprises a high bump density region projectively over the first semiconductor die.
11. The semiconductor package structure of claim 10 , wherein the active surface of the second semiconductor die further comprises a low bump density region projectively over the conductive element.
12. The semiconductor package structure of claim 10 , wherein the second semiconductor die overhangs from the second RDL.
13. The semiconductor package structure of claim 10 , further comprising an optical fiber optically coupled to the waveguide layer of the second semiconductor die.
14. The semiconductor package structure of claim 13 , wherein the optical fiber is disposed over the second semiconductor die.
15. A fan-out package structure, comprising:
a substrate;
a first package over the substrate, the first package comprising:
a first semiconductor die;
a fan-out redistribution layer (RDL) electrically coupled to an active surface of the first semiconductor die;
a high bump density region on the first semiconductor die; and
a low bump density region adjacent to the first semiconductor die,
wherein the fan-out RDL electrically couples the high bump density region and the low bump density region; and
a second package over the first package, wherein the second package comprises:
a semiconductor die;
a high bump density region at an active surface of the second semiconductor die, corresponding to the high bump density region of the first package; and
a low bump density region at the active surface of the second semiconductor die, corresponding to the low bump density region of the first package.
16. The fan-out package structure of claim 15 , wherein the second package comprises a photonic integrated circuit.
17. The fan-out package structure of claim 15 , wherein the low bump density region of the first package comprises a conductive element.
18. The fan-out package structure of claim 15 , further comprising conducive terminals between the first package and the substrate, electrically coupling the active surface of the first semiconductor die to the substrate.