Array substrate, method of making array substrate and display device having sub-pixels with transparent etching layer

1. An array substrate comprising a plurality of pixels, each of the pixels comprising a plurality of sub-pixels,

wherein each of the plurality of sub-pixels comprises a base substrate, an insulating layer, a color filter layer, a planarization layer, and an organic light emitting unit,

wherein the insulating layer covers the base substrate, the insulating layer is provided with a first opening, at least a portion of the color filter layer is filled in the first opening, the planarization layer covers over the insulating layer and a surface of the color filter layer, and the organic light emitting unit is disposed on the planarization layer,

wherein each of the plurality of sub-pixels further comprises a transparent etching barrier layer between the color filter layer and the base substrate,

wherein the insulating layer comprises a buffer layer, an interlayer dielectric layer covering the buffer layer, and a passivation layer covering the interlayer dielectric layer, and

wherein a first sub-opening is provided in the buffer layer, a second sub-opening is provided in the interlayer dielectric layer, and a third sub-opening is provided in the passivation layer.

2. The array substrate according to claim 1 , wherein the first opening extends through the insulating layer.

3. The array substrate according to claim 1 , wherein the first opening extends into the insulating layer but does not extend through the insulating layer.

4. The array substrate according to claim 1 , wherein each of the plurality of sub-pixels further comprises a light shielding layer covering the base substrate, and a top gate thin film transistor, the top gate thin film transistor comprising a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulating layer.

5. A display panel, comprising the array substrate according to claim 1 .

6. A display device, comprising the display panel according to claim 5 .

7. An array substrate comprising a plurality of pixels, each of the pixels comprising a plurality of sub-pixels,

wherein each of the plurality of sub-pixels comprises a base substrate, an insulating layer, a color filter layer, a planarization layer, and an organic light emitting unit,

wherein the insulating layer covers the base substrate, the insulating layer is provided with a first opening, at least a portion of the color filter layer is filled in the first opening, the planarization layer covers over the insulating layer and a surface of the color filter layer, and the organic light emitting unit is disposed on the planarization layer,

wherein each of the plurality of sub-pixels further comprises a transparent etching barrier layer between the color filter layer and the base substrate,

wherein each of the plurality of sub-pixels further comprises a light shielding layer covering the base substrate, and a top gate thin film transistor, the top gate thin film transistor comprising a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulating layer,

wherein each of the plurality of sub-pixels further comprises a pixel capacitor, the pixel capacitor comprising a first electrically conductive layer and a second electrically conductive layer;

wherein the first electrically conductive layer covers the base substrate, the first electrically conductive layer is electrically connected to the drain electrode, and first electrically conductive layers of two adjacent ones of the plurality of sub-pixels are insulated from each other; and

wherein the second electrically conductive layer and the drain electrode cover a same layer, and the second electrically conductive layer is electrically connected to the gate electrode.

8. The array substrate according to claim 7 , wherein the light shielding layer covers the first electrically conductive layer and is electrically connected to the first electrically conductive layer, and the light shielding layer is electrically connected to the drain electrode.

9. The array substrate according to claim 7 , wherein each of the plurality of sub-pixels further comprises a passivation layer covering surfaces of the source electrode, the drain electrode and the second electrically conductive layer; and

the insulating layer comprises a buffer layer and the passivation layer, the buffer layer covering a surface of the light shielding layer, the planarization covering the passivation layer.

10. The array substrate according to claim 9 , wherein the organic light emitting unit comprises a transparent electrode, at least a portion of the transparent electrode covering the planarization layer, the transparent electrode being electrically connected to the first electrically conductive layer, the transparent electrode comprising a first region, and

wherein an orthographic projection of the first region on the base substrate at least partially overlaps with an orthographic projection of the second electrically conductive layer on the base substrate.

11. The array substrate according to claim 10 , wherein the planarization layer is provided with a second opening extending through the planarization layer, and the first region covers the passivation layer and is located in the second opening.

12. The array substrate according to claim 10 , wherein the organic light emitting unit further comprises an organic light emitting layer disposed on the transparent electrode and an electrode disposed on the organic light emitting layer.