NVDIMM serial interface for out-of-band management by a baseboard management controller and method therefor

1. An information handling system comprising:

a baseboard management controller (BMC);

a central processing unit (CPU); and

a non-volatile dual-inline memory module (NVDIMM) including:

a volatile memory device;

a non-volatile memory device;

a double data rate (DDR) interface to provide access to the volatile memory device by the CPU;

a first serial bus interface to access serial presence detect information; and

a second serial bus interface to provide side-band and out-of-band data transfer between the non-volatile memory device and the BMC,

wherein the first serial bus interface and the second serial bus interface are different than the DDR interface.

2. The information handling system of claim 1 , wherein the side-band data transfer comprises accessing data stored at the non-volatile memory independently of accesses of the volatile memory device using the DDR interface.

3. The information handling system of claim 1 , wherein the out-of-band data transfer comprises accessing data stored at the non-volatile memory device when a DDR memory controller included at the information handling system and coupled to the DDR interface is not operational.

4. The information handling system of claim 1 , wherein the BMC is configured to store a signed basic input/output system (BIOS) payload at the non-volatile memory device, the BIOS payload to update a BIOS image stored at a serial peripheral interface flash device included at the information handling system.

5. The information handling system of claim 1 , wherein the BMC is configured to provide cryptography services to authenticate information stored at the non-volatile memory device.

6. The information handling system of claim 1 , wherein the BMC is configured to store signed firmware corresponding to resource of the information handling system managed by the BMC at the non-volatile memory device.

7. The information handling system of claim 1 , wherein the BMC is configured to:

determine that selected firmware is not to be stored at a serial peripheral interface (SPI) flash device included at the information handling system; and

store the selected firmware at the non-volatile memory device.

8. The information handling system of claim 1 , wherein the BMC is configured to store authenticated operating system components at the non-volatile memory device, the components accessible by an operating system kernel-level driver.

9. The information handling system of claim 1 , wherein the BMC is configured to store status log information at the non-volatile memory device.

10. The information handling system of claim 1 , wherein the BMC provides a root of trust at the information handling system by authenticating an initial boot block at a serial peripheral interface flash device included at the information handling system.

11. A method comprising:

providing a double data rate (DDR) interface at a non-volatile dual-inline memory module (NVDIMM), the DDR bus interface for accessing a volatile memory device included at the NVDIMM by a central processing unit included at an information handling system;

providing a first serial bus interface at the (NVDIMM for accessing serial presence detect information at the NVDIMM; and

providing a second serial bus interface at the NVDIMM for accessing a non-volatile memory device included at the NVDIMM by a baseboard management controller (BMC) at the information handling system, the second serial bus interface providing side-band and out-of-band data transfer of information between the non-volatile memory device and the BMC,

wherein the first serial bus interface and the second serial bus interface are different than the DDR interface.

12. The method of claim 11 , wherein the side-band data transfer comprises accessing data stored at a non-volatile memory device independently of accesses of the volatile memory device using a double data rate interface.

13. The method of claim 11 , wherein the out-of-band data transfer comprises accessing data stored at a non-volatile memory device at the NVDIMM when a double data rate memory controller included at an information handling system and coupled to the double data rate interface at the NVDIMM is not operational.

14. The method of claim 11 , wherein the BMC is configured to store a signed basic input/output system (BIOS) payload at a non-volatile memory device at the NVDIMM, the BIOS payload to update a BIOS image stored at a serial peripheral interface flash device included at the information handling system.

15. The method of claim 11 , wherein the BMC is configured to provide cryptography services to authenticate information stored at a non-volatile memory device at the NVDIMM.

16. The method of claim 11 , wherein the BMC is configured to store signed firmware corresponding to resource of an information handling system managed by the BMC at a non-volatile memory device at the NVDIMM.

17. The method of claim 11 , wherein the BMC is configured to:

determine that selected firmware is not to be stored at a serial peripheral interface flash device included at an information handling system; and

storing the selected firmware at a non-volatile memory device at the NVDIMM.

18. The method of claim 11 , wherein the BMC is configured to store authenticated operating system components at a non-volatile memory device at the NVDIMM, the components accessible by an operating system kernel-level driver.

19. The method of claim 11 , wherein the BMC provides a root of trust at an information handling system by authenticating an initial boot block at a serial peripheral interface flash device included at the information handling system.

20. A non-volatile dual-inline memory module comprising:

a non-volatile memory device;

a dynamic random access memory device;

a double data rate interface to access the dynamic random access memory device;

a first serial bus interface to provide access to serial presence detect information; and

a second serial bus interface to provide side-band or out-of-band access to the non-volatile memory device by a baseboard management controller,

wherein the first serial bus interface and the second serial bus interface are different than the double data rate interface.