Vector maximum and minimum with indexing
A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
1. A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction, the method comprising:
specifying, in respective fields of the vector maximum with indexing instruction, a first source register containing the first source data, a second source register containing the second source data, a destination register to store compared data, and a predicate register, wherein each of the first and second source registers, the destination register, and the predicate register comprises a plurality of lanes; and
executing the vector maximum with indexing instruction, wherein executing the vector maximum with indexing instruction further comprises, for each lane in the first source register and a corresponding lane in the second source register:
comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value;
storing the maximum value in a corresponding lane of the destination register;
asserting a corresponding lane of the predicate register as a result of the maximum value being from the first source register; and
de-asserting the corresponding lane of the predicate register as a result of the maximum value being from the second source register.
2. The method of claim 1 , wherein the destination register comprises the second source register.
3. The method of claim 1 , wherein the first and second source data each comprise a 512-bit vector.
4. The method of claim 3 , wherein the lanes of the first and second source registers comprise 8-bit lanes.
5. The method of claim 4 , wherein the value in each 8-bit lane is a signed value.
6. The method of claim 4 , wherein the corresponding lane of the predicate register comprises a single bit.
7. A data processor, comprising:
a first source register configured to contain first source data;
a second source register configured to contain second source data;
a destination register; and
a predicate register;
wherein each of the first and second source registers, the destination register, and the predicate register comprise a plurality of lanes;
wherein, in response to execution of a single vector maximum with indexing instruction, the data processor is configured to:
compare a value in a lane of the first source register to a value in a corresponding lane of the second source register to identify a maximum value;
store the maximum value in a corresponding lane of the destination register;
assert a corresponding lane of the predicate register as a result of the maximum value being from the first source register; and
de-assert the corresponding lane of the predicate register as a result of the maximum value being from the second source register.
8. The data processor of claim 7 , wherein the destination register comprises the second source register.
9. The data processor of claim 7 , wherein the first and second source data each comprise a 512-bit vector.
10. The data processor of claim 9 , wherein the lanes of the first and second source registers comprise 8-bit lanes.
11. The data processor of claim 10 wherein the value in each 8-bit lane is a signed value.
12. The data processor of claim 10 , wherein the corresponding lane of the predicate register comprises a single bit.
13. A method to compare first and second source data in a processor in response to a vector minimum with indexing instruction, the method comprising:
specifying, in respective fields of the vector minimum with indexing instruction, a first source register containing the first source data, a second source register containing the second source data, a destination register to store compared data, and a predicate register, wherein each of the first and second source registers, the destination register, and the predicate register comprises a plurality of lanes; and
executing the vector minimum with indexing instruction, wherein executing the vector minimum with indexing instruction further comprises, for each lane in the first source register and a corresponding lane in the second source register:
comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a minimum value;
storing the minimum value in a corresponding lane of the destination register;
asserting a corresponding lane of the predicate register as a result of the minimum value being from the first source register; and
de-asserting the corresponding lane of the predicate register as a result of the minimum value being from the second source register.
14. The method of claim 13 , wherein the destination register comprises the second source register.
15. The method of claim 13 , wherein the first and second source data each comprise a 512-bit vector.
16. The method of claim 15 , wherein the lanes of the first and second source registers comprise 8-bit lanes.
17. The method of claim 16 , wherein the value in each 8-bit lane is a signed value.
18. The method of claim 16 , wherein the corresponding lane of the predicate register comprises a single bit.
19. A data processor, comprising:
a first source register configured to contain first source data;
a second source register configured to contain second source data;
a destination register; and
a predicate register;
wherein each of the first and second source registers, the destination register, and the predicate register comprise a plurality of corresponding lanes;
wherein, in response to execution of a single vector minimum with indexing instruction, the data processor is configured to:
compare a value in a lane of the first source register to a value in a corresponding lane of the second source register to identify a minimum value;
store the minimum value in a corresponding lane of the destination register;
assert a corresponding lane of the predicate register as a result of the minimum value being from the first source register; and
de-assert the corresponding lane of the predicate register as a result of the minimum value being from the second source register.
20. The data processor of claim 19 , wherein the destination register comprises the second source register.
21. The data processor of claim 19 , wherein the first and second source data each comprise a 512-bit vector.
22. The data processor of claim 21 , wherein the lanes of the first and second source registers comprise 8-bit lanes.
23. The data processor of claim 22 , wherein the value in each 8-bit lane is a signed value.
24. The data processor of claim 22 , wherein the corresponding lane of the predicate register comprises a single bit.