Memory device for programming dummy pages, memory controller for controlling the memory device and memory system having the same

1. A memory controller comprising:

a central processing unit configured to output a read command for checking an erase state of a selected storage block in response to a program request from a host, determine a number of pages to store dummy data in the selected storage block based on read data obtained by the read command, and output a program command to store the dummy data and user data corresponding to the program request in the selected storage block; and

a memory interface configured to generate the dummy data corresponding to the number of pages, and output the dummy data and the user data,

wherein the read data includes information indicating a voltage range, among a plurality of reference voltage ranges,

wherein threshold voltages of memory cells included in the selected storage block are within the voltage range, and

wherein the dummy data and the user data are stored in separate pages, respectively.

2. The memory controller of claim 1 , wherein the central processing unit includes:

a received request detector configured to output a read sub-request, an erase sub-request, or a program sub-request in response to a request received from the host; and

a command generator configured to output the program command, the read command or an erase command in response to the program sub-request, the read sub-request or the erase sub-request.

3. The memory controller of claim 2 , wherein the received request detector:

when the request received from the host is the program request or a read request, outputs the read sub-request,

when the request received from the host is an erase request, outputs the erase sub-request, and

when a program signal is received, outputs the program sub-request.

4. The memory controller of claim 3 , wherein the central processing unit includes an erase state table manager configured to output the number of pages and the program signal according to threshold voltage information of the selected storage block, which corresponds to the erase state.

5. The memory controller of claim 4 , wherein the erase state table manager includes:

registers having the plurality of reference voltage ranges and indicating the number of pages respectively allocated to the plurality of reference voltage ranges which include threshold voltages; and

a circuit configured to output the program signal when the threshold voltage information is received.

6. The memory controller of claim 5 , wherein the number of pages includes a value where the number of pages decreases when the threshold voltages of the memory cells included in the selected storage block increases.

7. The memory controller of claim 2 , wherein the memory interface includes:

a command queue manager configured to queue the commands received from the command generator, and sequentially output queued commands;

a parameter register configured to store voltages and time values, which are set to perform program, read, and erase operations, and output parameter information including information of setting values suitable for each operation;

a data manager configured to temporarily store and output the user data, and selectively generate and output the dummy data according to the number of pages; and

an address buffer configured to output a physical address of the selected storage block, which corresponds to a logical address received from the host, or output an address of the selected storage block when the received logic address does not exist.

8. The memory controller of claim 7 , wherein the data manager includes:

a data buffer configured to temporarily store and output the user data; and

a dummy data generator configured to generate and output the dummy data.

9. The memory controller of claim 7 , wherein the address buffer:

when a read request is received from the host, outputs the physical address of the selected storage block, which corresponds to the received logical address, together with the read request, and

when a program request is received from the host, outputs the physical address of the selected storage block.

10. A memory system comprising:

a memory device configured to store data; and

a memory controller configured to, when a program request is received from a host, determine a number of pages to store dummy data in a selected storage block based on read data obtained by a read command for checking an erase state of the selected storage block among unselected pages of the selected storage block, and store the dummy data and user data corresponding to the program request in the selected storage block,

wherein the read data includes information indicating a voltage range, among a plurality of reference voltage ranges,

wherein threshold voltages of memory cells included in the selected storage block are within the voltage range, and

wherein the dummy data and the user data are stored in separate pages, respectively.

11. The memory system of claim 10 , wherein the memory controller reads a selected page of the selected storage block, and determines the erase state of the selected storage block, based on a read result, so as to check the erase state of the selected storage block when the program request is received from the host.

12. The memory system of claim 11 , wherein the memory controller, based on the read result,

when threshold voltages of erased memory cells included in the selected storage block are greater than a reference voltage, does not select the pages, and

when the threshold voltages of the erased memory cells included in the selected storage block are less than the reference voltage, selects the pages.

13. The memory system of claim 12 , wherein the pages are selected among the unselected pages to which the user data is not stored in the selected storage block.

14. The memory system of claim 11 , wherein, among a plurality of pages included in the selected storage block,

memory cells of the other pages except the separate pages in which the user data and the dummy data are stored maintain the erase state.

15. The memory system of claim 12 , wherein, when the threshold voltages of the erased memory cells included in the selected storage block are less than the reference voltage, the memory controller selects the number of pages according to threshold voltage levels of the memory cells.

16. The memory system of claim 15 , wherein the memory controller sets a plurality of different reference voltages, and selects the number of pages, based on which range the threshold voltages of the erased memory cells are included in.

17. The memory system of claim 16 , wherein the memory controller:

increases the number of pages when the threshold voltages of the erased memory cells decrease; and

decreases the number of pages when the threshold voltages of the erased memory cells increase.

18. The memory system of claim 16 , wherein the memory controller

performs a dummy program operation on some pages according to the number of pages.