Implementation of load acquire/store release instructions using load/store operation with DMB operation
A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.
1. A non-transitory computer-readable medium having stored thereon a memory access instruction which, when executed by a processor, causes the processor to:
perform a first memory access operation, the first memory access operation comprising at least one first micro-operation that is a memory load operation;
perform a first data memory barrier operation associated with the first memory access operation, the first data memory barrier operation comprising at least one second micro-operation, the first data memory barrier operation imposing an order of operations on all prior memory access operations before the first data memory barrier operation, all the prior memory access operations including the first memory access operation.
2. The non-transitory computer-readable medium of claim 1 , wherein the first memory access operation is performed and completed before the first data memory barrier operation based on the order of operations.
3. The non-transitory computer-readable medium of claim 1 , wherein the memory access instruction is a load with acquire instruction.
4. The non-transitory computer-readable medium of claim 1 , wherein the first memory access operation is configured to specify an address for accessing a data from a memory.
5. The non-transitory computer-readable medium of claim 1 , wherein the memory access instruction, when executed by the processor, causes the processor to:
perform a second data memory barrier operation associated with an additional memory access operation, the second data memory barrier operation comprising at least one third micro-operation,
wherein the second data memory barrier operation enforces an ordering constraint ensuring that the additional memory access operation is completed before performing the second data memory barrier operation.
6. The non-transitory computer-readable medium of claim 5 , wherein the first data memory barrier operation is performed before the additional memory access operation and the second data memory barrier operation is performed following the additional memory access operation based on the ordering constraint.
7. The non-transitory computer-readable medium of claim 5 , wherein the additional memory access instruction comprises a store with release instruction.
8. A processor configured to perform computer-executable instructions configured to:
perform a first memory access operation, the first memory access operation comprising at least one first micro-operation that is a memory load operation; and
perform a first data memory barrier operation associated with the first memory access operation, the first data memory barrier operation comprising at least one second micro-operation, the first data memory barrier operation imposing an order of operations on all prior memory access operations before the first data memory barrier operation, all the prior memory access operations including the first memory access operation.
9. The processor of claim 8 , wherein the processor is configured to perform and complete the first memory access operation before the first data memory barrier operation based on the order of operations.
10. The processor of claim 8 , wherein the memory access instruction is a load with acquire instruction.
11. The processor of claim 8 , wherein the memory access instruction, when executed by the processor, causes the processor to:
perform a second data memory barrier operation associated with an additional memory access operation, the second data memory barrier operation comprising at least one third micro-operation,
wherein the second data memory barrier operation enforces an ordering constraint ensuring that the additional memory access operation is completed before performing the second data memory barrier operation.
12. The processor of claim 11 , wherein the first data memory barrier operation is performed before the additional memory access operation and the second data memory barrier operation is performed following the additional memory access operation based on the ordering constraint.
13. The processor of claim 11 , wherein the additional memory access instruction comprises a store with release instruction.
14. The processor of claim 8 , wherein the processor is a reduced instruction set computing (RISC) processor.
15. The processor of claim 14 , wherein the processor is an advanced RISC machine (ARM) processor.
16. A computer-implemented method comprising:
performing a first memory access operation, the memory access operation comprising at least one first micro-operation with a memory load operation; and
performing a first data memory barrier operation associated with the first memory access operation, the first data memory barrier operation comprising at least one second micro-operation, the first data memory barrier operation imposing an order of operations on all prior memory access operations before the first data memory barrier operation, all the prior memory access operations including the first memory access operation.
17. The computer-implemented method of claim 16 , wherein the first memory access operation is performed and completed before the first data memory barrier operation based on the order of operations.
18. The computer-implemented method of claim 16 , wherein the first data memory barrier operation is associated with the first memory access operation via a memory access instruction, wherein the memory access instruction is a load with acquire instruction.
19. The computer-implemented method of claim 16 , wherein the first data memory barrier operation is associated with the first memory access operation via a memory access instruction, wherein the memory access instruction, when executed by the processor, causes the processor to:
perform a second data memory barrier operation associated with an additional memory access operation, the second data memory barrier operation comprising at least one third micro-operation,
wherein the second data memory barrier operation enforces an ordering constraint ensuring that the additional memory access operation is completed before performing the second data memory barrier operation.
20. The computer-implemented method of claim 19 , wherein the first data memory barrier operation is performed before the additional memory access operation and the second data memory barrier operation is performed following the additional memory access operation based on the ordering constraint.
21. The computer-implemented method of claim 16 , wherein the first data memory barrier operation is associated with the first memory access operation via a memory access instruction,
wherein the memory access instruction, when executed by the processor, causes the processor to:
perform an additional memory access operation comprising at least one fourth micro-operation,
wherein the first data memory barrier operation enforces an ordering constraint of the order of operations on at least one subsequent memory access operation executed after the first data memory barrier operation, the at least one subsequent memory access operation including the additional memory access operation.
22. The computer-implemented method of claim 21 , wherein the first memory access operation is a load with acquire operation and the additional memory access operation is a store operation.
23. The computer-implemented method of claim 21 , wherein the first data memory barrier operation defines the order of operations for all prior memory access operations and the at least one subsequent memory access operation.
24. The computer-implemented method of claim 16 , wherein all the prior memory access operations include an additional load operation.