IP Library Granted Patent US 11,177,134
Granted Patent B2
US 11,177,134 · App. 16/424,694 · Granted Nov 16, 2021

Conductive pattern and method for manufacturing the same, thin film transistor, display substrate, and display device

Inventors: Jianguo Wang (Beijing, CN); Zhanfeng Cao (Beijing, CN); Haixu Li (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
H01L21/2855C23C14/025C23C14/042C23C14/18C23C14/5873H01L21/32139H01L21/76885H01L23/49H01L23/53238H01L23/562H01L27/124H01L27/1244H01L27/1288H01L29/401H01L29/42376H01L29/45H01L29/458H01L29/4908
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Quick Facts
Patent No.
US 11,177,134
App. No.
16/424,694
Granted
Nov 16, 2021
Kind
B2
Abstract

A conductive pattern and a method for manufacturing the same, a thin film transistor, a display substrate and a display device are provided. The method includes: step A, forming a metal layer on a base substrate; step B, forming a first conductive buffer layer on the metal layer; step C, patterning the metal layer and the first conductive buffer layer to form a conductive sub-pattern; and performing steps A to C repeatedly for N times to form N conductive sub-patterns that are stacked on the base substrate. The conductive pattern comprises the N conductive sub-patterns, and N is a positive integer greater than 1.

Claims (25)

1. A method for manufacturing a conductive pattern, comprising:

providing a base substrate;

step A: forming a metal layer;

step B: forming a first conductive buffer layer on the metal layer;

step C: patterning the metal layer and the first conductive buffer layer to form a conductive sub-pattern; and

performing steps A to C repeatedly for N times to form N conductive sub-patterns that are stacked on the base substrate, wherein the conductive pattern comprises the N conductive sub-patterns, and N is a positive integer greater than 1;

wherein an orthographic projection of the n-th formed conductive sub-pattern onto the base substrate falls within an orthographic projection of the (n−1)-th formed conductive sub-pattern onto the base substrate, and n is a positive integer greater than 1, and is smaller than or equal to N;

wherein the step A comprises:

forming the metal layer by a sputtering process using Cu;

wherein the step C comprises:

forming a photoresist on the first conductive buffer layer;

exposing and developing the photoresist using a mask plate, and then forming a pattern of the photoresist;

etching the second conductive buffer layer, the metal layer and the first conductive buffer layer using the pattern of the photoresist as a mask to form a first conductive sub-pattern and stripping the remaining photoresist;

sputtering a second metal layer on the base substrate on which the first conductive sub-pattern is formed;

further forming the first conductive buffer layer on the second metal layer; and

patterning the second metal layer and the first conductive buffer layer to form a second conductive sub-pattern;

wherein an area of a mask plate of the second conductive sub-pattern is smaller than an area of a mask plate of the first conductive sub-pattern.

2. The method according to claim 1 , wherein prior to the step A, the method further comprises:

forming a second conductive buffer layer on the base substrate, wherein the second conductive buffer layer is below a first conductive sub-pattern of the N conductive sub-patterns, and the first conductive sub-pattern is closest to the base substrate relative to other conductive sub-patterns of the N conductive sub-patterns.

3. The method according to claim 1 , wherein the step B comprises:

forming the first conductive buffer layer using at least one of Mo, MoTi, MoNb, MoAl, MoSb, MoW, MoNi, MoNbSn or MoNiTi.

4. The method according to claim 2 , wherein the forming the second conductive buffer layer comprises:

forming the second conductive buffer layer using at least one of Mo, MoTi, MoNb, MoAl, MoSb, MoW, MoNi, MoNbSn or MoNiTi.

5. The method according to claim 1 , wherein the step C comprises:

coating a photoresist on the first conductive buffer layer, exposing the photoresist using a mask plate, and developing to form the conductive sub-pattern.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: BOE TECHNOLOGY GROUP CO., LTD.
To: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Reel/Frame 060826/0252 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2019
From: WANG, JIANGUO; CAO, ZHANFENG; LI, HAIXU
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049302/0572 →
Priority Claims (1)
CN 201811406097.0 · Nov 23, 2018 · national
Continuity (1)
Related Publication 20200168461A1 · May 28, 2020