Quantum error-correction in microwave integrated quantum circuits
In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.
1. A quantum error-correction method comprising:
applying a first set of two-qubit gates to qubits in a lattice cell, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;
applying a second, different set of two-qubit gates to the qubits in the lattice cell; and
after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and
determining a parity of the measurement outcomes.
2. The method of claim 1 , wherein the two-qubit gates in the first set and the two-qubit gates in the second set are applied to respective pairs of qubits in the lattice cell, and each respective pair includes one of the data qubits and one of the ancilla qubits.
3. The method of claim 1 , wherein each of the two-qubit gates in the first set and each of the two-qubit gates in the second set is applied to a distinct pair of the qubits in the lattice cell.
4. The method of claim 1 , wherein applying a first set of two-qubit gates comprises applying a first set of controlled-not gates, and applying a second set of two-qubit gates comprises a second, different set of controlled-not gates.
5. The method of claim 4 , wherein the controlled-not gates in the first set and the controlled-not gates in the second set are applied to respective pairs of devices in the lattice cell, with one of the data qubits as the control and one of the ancilla qubits as the target.
6. The method of claim 4 , wherein:
the first set of controlled-not gates comprises:
a controlled-not gate with a first data qubit as the control and a first ancilla qubit as the target;
a controlled-not gate with a second data qubit as the control and a second ancilla qubit as the target;
a controlled-not gate with a third data qubit as the control and a third ancilla qubit as the target; and
a controlled-not gate with a fourth data qubit as the control and a fourth ancilla qubit as the target; and
the second set of controlled-not gates comprises:
a controlled-not gate with the first data qubit as the control and the fourth ancilla qubit as the target;
a controlled-not gate with the second data qubit as the control and the first ancilla qubit as the target;
a controlled-not gate with the third data qubit as the control and the second ancilla qubit as the target; and
a controlled-not gate with the fourth data qubit as the control and the third ancilla qubit as the target.
7. The method of claim 4 , wherein at least one of the controlled-not gates is applied to qubits defined respectively by a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to an operating frequency of the transmon device.
8. The method of claim 4 , wherein at least one of the controlled-not gates is applied to qubits defined respectively a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to the |1 →|2 transition frequency of the transmon device.
9. The method of claim 1 , wherein the lattice cell comprises:
transmon devices that define the data qubits; and
fluxonium devices that define the ancilla qubits.
10. The method of claim 1 , wherein the lattice cell comprises:
fluxonium devices that define the data qubits; and
transmon devices that define the ancilla qubits.
11. The method of claim 1 , wherein the lattice cell comprises:
a first group of fluxonium devices that define the data qubits; and
a second group of fluxonium devices that define the ancilla qubits.
12. The method of claim 1 , wherein the lattice cell comprises:
a first group of transmon devices that define the data qubits; and
a second group of transmon devices that define the ancilla qubits.
13. The method of claim 1 , wherein a rectilinear lattice comprises the lattice cell, and the parity is used for quantum error-correction in a surface code applied to the rectilinear lattice.
14. The method of claim 1 , wherein a rectilinear lattice comprises the lattice cell, and the parity is used for quantum error-correction in a color code applied to the rectilinear lattice.
15. A quantum computing system comprising:
a quantum processor cell comprising a device lattice;
a control system communicably coupled to the quantum processor cell to control the device lattice, the control system configured to:
apply a first set of two-qubit gates to qubits in a lattice cell in the device lattice, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;
apply a second, different set of two-qubit gates to the qubits in the lattice cell; and
after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and
determine a parity of the measurement outcomes.
16. The quantum computing system of claim 15 , wherein the two-qubit gates in the first set and the two-qubit gates in the second set are applied to respective pairs of qubits in the lattice cell, and each respective pair includes one of the data qubits and one of the ancilla qubits.
17. The quantum computing system of claim 15 , wherein each of the two-qubit gates in the first set and each of the two-qubit gates in the second set is applied to a distinct pair of the qubits in the lattice cell.
18. The quantum computing system of claim 15 , wherein applying a first set of two-qubit gates comprises applying a first set of controlled-not gates, and applying a second set of two-qubit gates comprises a second, different set of controlled-not gates.
19. The quantum computing system of claim 18 , wherein the controlled-not gates in the first set and the controlled-not gates in the second set are applied to respective pairs of devices in the lattice cell, with one of the data qubits as the control and one of the ancilla qubits as the target.
20. The quantum computing system of claim 18 , wherein:
the first set of controlled-not gates comprises:
a controlled-not gate with a first data qubit as the control and a first ancilla qubit as the target;
a controlled-not gate with a second data qubit as the control and a second ancilla qubit as the target;
a controlled-not gate with a third data qubit as the control and a third ancilla qubit as the target; and
a controlled-not gate with a fourth data qubit as the control and a fourth ancilla qubit as the target; and
the second set of controlled-not gates comprises:
a controlled-not gate with the first data qubit as the control and the fourth ancilla qubit as the target;
a controlled-not gate with the second data qubit as the control and the first ancilla qubit as the target;
a controlled-not gate with the third data qubit as the control and the second ancilla qubit as the target; and
a controlled-not gate with the fourth data qubit as the control and the third ancilla qubit as the target.