Digital-to-analog converter with integrated comb filter

1. A system comprising:

a digital-to-analog conversion circuit (DAC) operable to convert an input digital signal to an output analog signal, wherein the DAC comprises:

a digital signal processing circuit operable to:

process the input digital signal according to a first transfer function to generate a first processed digital signal; and

process the input digital signal according to a second transfer function to generate a second processed digital signal;

a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal;

a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal;

a combiner circuit,

a first switching circuit operable to connect the first intermediate analog signal to a first input of the combiner circuit when a clock signal is in a first state and disconnect the first intermediate analog signal from the first input of the combiner circuit when the clock signal is in a second state; and

a second switching circuit operable to connect the second intermediate analog signal to a second input of the combiner circuit when the clock signal is in the second state and disconnect the second intermediate analog signal from the second input of the combiner circuit when the clock signal is in the first state, wherein an output of the combiner circuit is the output analog signal.

2. The system of claim 1 , comprising one or more transfer-function-configuration registers, wherein the first transfer function and the second transfer function are determined based on contents of the one or more transfer-function-configuration registers.

3. The system of claim 2 , wherein the contents of the one or more transfer-function-configuration registers are writable during runtime of the DAC.

4. The system of claim 2 , comprising:

monitoring circuitry operable to determine a characteristic of a network into which the output analog signal is to be transmitted; and

control circuitry operable to update the contents of the one or more transfer-function-configuration registers based on the determined characteristic.

5. The system of claim 2 , wherein:

the first transfer function corresponds to a first polynomial;

the second transfer function corresponds to a second polynomial; and

the one or more transfer-function-configuration registers determine a degree of the first polynomial and a degree of the second polynomial.

6. The system of claim 2 , wherein the contents of the one or more transfer-function-configuration registers are writable during runtime of the DAC.

7. The system of claim 2 , comprising nonvolatile memory in which is stored one or more settings of the one or more transfer-function-configuration registers.

8. The system of claim 7 , comprising control circuitry operable to read the one or more settings from the nonvolatile memory and write the one or more settings to the one or more transfer-function-configuration registers.

9. The system of claim 1 , wherein the digital signal processing circuit comprises one or more delay circuits, one or more adder circuits and one or more divide-by-two circuits.

10. A method for converting an input digital signal to an analog output signal, the method comprising:

processing, by digital signal processing circuitry of a digital to analog converter circuit (DAC), the input digital signal according to a first transfer function to generate a first processed digital signal;

processing, by the digital signal processing circuitry, the input digital signal according to a second transfer function to generate a second processed digital signal;

converting, by a first unit DAC, the first processed digital signal to a first intermediate analog signal;

converting, by a second unit DAC, the second processed digital signal to a second intermediate analog signal;

connecting, by a first switching circuit, the first intermediate analog signal to a first input of a combiner circuit when a clock signal is in a first state;

disconnecting, by the first switching circuit, the first intermediate analog signal from the first input of the combiner circuit when the clock signal is in a second state;

connecting, by a second switching circuit, the second intermediate analog signal to a second input of the combiner circuit when the clock signal is in the second state; and

disconnecting, by the second switching circuit, the second intermediate analog signal from the second input of the combiner circuit when the clock signal is in the first state, wherein an output of the combiner circuit is the analog output signal.

11. The method of claim 10 , comprising determining, by the digital signal processing circuitry, the first transfer function and the second transfer function based on contents of the one or more transfer-function-configuration registers.

12. The method of claim 11 , comprising writing, by control circuitry, the contents of the one or more transfer-function-configuration registers during runtime of the DAC.

13. The method of claim 11 , comprising:

determining, by monitoring circuitry, a characteristic of a network into which the output analog signal is to be transmitted; and

updating, by control circuitry, the contents of the one or more transfer-function-configuration registers based on the determined characteristic.

14. The method of claim 11 , wherein:

the first transfer function corresponds to a first polynomial;

the second transfer function corresponds to a second polynomial; and

the one or more transfer-function-configuration registers determine a degree of the first polynomial and a degree of a second polynomial.

15. The method of claim 12 , comprising writing, by control circuitry, the contents of the one or more transfer-function-configuration registers during runtime of the DAC.

16. The method of claim 11 , wherein one or more settings of the one or more transfer-function-configuration registers are stored in nonvolatile memory.

17. The method of claim 16 , comprising reading, by control circuitry, the one or more settings from the nonvolatile memory and writing the one or more settings to the one or more transfer-function-configuration registers.

18. The method of claim 10 , wherein the digital signal processing circuit comprises one or more delay circuits, one or more adder circuits and one or more divide-by-two circuits.