System and method to reduce address range scrub execution time in non-volatile dual inline memory modules

1. An information handling system, comprising:

a first non-volatile dual in-line memory module (NVDIMM) configured to instantiate a first partition of non-volatile memory and a second partition of non-volatile memory, the first partition being a reserved partition that is not accessible to an operating system instantiated on the information handling system, and the second partition being accessible to the operating system; and

a processor configured to:

detect a first bad memory location in the second partition;

store a first system physical address (SPA) associated with the first bad memory location to a system bad memory locations list; and

store a first DIMM physical address (DPA) of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

2. The information handling system of claim 1 , wherein the first SPA represents a location of the first bad memory location within a memory architecture of the information handling system, and wherein the first DPA represents a location of the first bad memory location within a the first NVDIMM.

3. The information handling system of claim 1 , wherein the processor is further configured to:

convert the first SPA to the first DPA before storing the first DPA to the NVDIMM bad memory locations list.

4. The information handling system of claim 1 , further comprising:

a second NVDIMM configured to instantiate a third partition of non-volatile memory and a fourth partition of non-volatile memory, the third partition being a reserved partition that is not accessible to the operating system, and the fourth partition being accessible to the operating system;

wherein the processor is further configured to;

detect a second bad memory location in the fourth partition;

store a second SPA of the second bad memory location to the system bad memory locations list; and

store a second DPA of the second bad memory location to a second NVDIMM bad memory locations list in the third partition.

5. The information handling system of claim 1 , wherein the processor is further configured to:

read a second NVDIMM bad memory location list from a third partition in a second NVDIMM; and

determine whether or not the second NVDIMM bad memory locations list matches the system bad memory locations list.

6. The information handling system of claim 5 , wherein the processor is further configured to:

convert DPAs from the second NVDIMM bad memory locations list SPAs, wherein determining whether or not the second NVDIMM bad memory locations list matches the system bad memory locations list is based upon the converted SPAs.

7. The information handling system of claim 6 , wherein the processor is further configured to:

determine that the second NVDIMM is a newly installed NVDIMM into the information handling system when the second NVDIMM bad memory locations list does not match the system bad memory locations list.

8. The information handling system of claim 7 , wherein the processor is further configured to:

execute an address range scrub process on the first and second NVDIMMs in response to determining that the second NVDIMM is a newly installed NVDIMM.

9. The information handling system of claim 6 , wherein the processor is further configured to:

determine that the second NVDIMM is the first NVDIMM when the second NVDIMM bad memory locations list matches the system bad memory locations list.

10. A method, comprising:

providing, on a first non-volatile dual in-line memory module (NVDIMM), a first partition of non-volatile memory, wherein the first partition is a reserved partition that is not accessible to an operating system instantiated on the information handling system;

providing, on the first NVDIMM, a second partition of non-volatile memory, wherein the second partition is accessible to the operating system;

detecting, by a processor of the information handling system, a first bad memory location in the second partition;

storing, by the processor, a first system physical address (SPA) associated with the first bad memory location to a system bad memory locations list; and

storing, by the processor, a first DIMM physical address (DPA) of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

11. The method of claim 10 , wherein the first SPA represents a location of the first bad memory location within a memory architecture of the information handling system, and wherein the first DPA represents a location of the first bad memory location within a the first NVDIMM.

12. The method of claim 10 , further comprising:

converting, by the processor, the first SPA to the first DPA before storing the first DPA to the NVDIMM bad memory locations list.

13. The method of claim 10 , further comprising:

providing, on a second NVDIMM, a third partition of non-volatile memory, wherein the third partition is a reserved partition that is not accessible to the operating system;

providing, on the second NVDIMM, a fourth partition of non-volatile memory, wherein the fourth partition is accessible to the operating system;

detecting, by the processor, a second bad memory location in the fourth partition;

storing, by the processor, a second SPA of the first bad memory location to the system bad memory locations list; and

storing, by the processor, a second DPA of the second bad memory location to a second NVDIMM bad memory locations list in the third partition.

14. The method of claim 10 , further comprising:

reading, by the processor, a second NVDIMM bad memory location list from a third partition in a second NVDIMM; and

determining, by the processor, whether or not the second NVDIMM bad memory locations list matches the system bad memory locations list.

15. The method of claim 14 , further comprising:

converting, by the processor, DPAs from the second NVDIMM bad memory locations list SPAs, wherein determining whether or not the second NVDIMM bad memory locations list matches the system bad memory locations list is based upon the converted SPAs.

16. The method of claim 15 , further comprising:

determining, by the processor, that the second NVDIMM is a newly installed NVDIMM into the information handling system when the second NVDIMM bad memory locations list does not match the system bad memory locations list.

17. The method of claim 16 , further comprising:

Executing, by the processor, an address range scrub process on the first and second NVDIMMs in response to determining that the second NVDIMM is a newly installed NVDIMM.

18. The method of claim 16 , further comprising:

determining, by the processor, that the second NVDIMM is the first NVDIMM when the second NVDIMM bad memory locations list matches the system bad memory locations list.

19. An information handling system, comprising:

a DC persistent memory module (DCPMM) configured to instantiate a first partition of non-volatile memory and a second partition of non-volatile memory, the first partition being a reserved partition that is not accessible to an operating system instantiated on the information handling system and including a first region and a second region, and the second partition being accessible to the operating system; and

a processor configured to;

detect a bad memory location in the second partition;

store a system physical address (SPA) associated with the bad memory location to a system bad memory locations list, the first SPA being within a SPA-space of the information handling system;

convert the SPA to a DIMM physical address of the bad memory location; and

store the DPA to a DCPMM bad memory locations list in the first partition.

20. The information handling system of claim 19 , wherein the SPA represents a location of the bad memory location within a memory architecture of the information handling system, and wherein the DPA represents a location of the bad memory location within a the DCPMM.