Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor
A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.
1. A semiconductor structure comprising:
a first digit line;
a first transistor coupled to and elevationally-extending upwardly relative to the first digit line;
a first capacitor having an electrode above and coupled to the first transistor;
a second capacitor sharing a common plate with the first capacitor and having an electrode;
a second transistor coupled to and elevationally-extending upwardly relative to the electrode of the second capacitor; and
a second digit line above and coupled to the second transistor.
2. The semiconductor structure of claim 1 wherein,
the first and second digit lines extend in a first direction; and
the common plate of the first and second capacitors extends in a second direction that is orthogonal to the first direction.
3. The semiconductor structure of claim 2 wherein a gate of the first transistor and a gate of the second transistor also extend in the second direction.
4. The semiconductor structure of claim 1 , wherein,
the first and second digit lines extend in a first direction;
the common plate of the first and second capacitors also extends in the first direction; and
a gate of the first transistor extends in a second direction that is orthogonal to the first direction.
5. The semiconductor structure of claim 4 wherein a gate of the second transistor also extends in the second direction.
6. The semiconductor structure of claim 1 wherein the common plate is taller than it is wide.
7. The semiconductor structure of claim 1 wherein the common plate is elongated vertically.
8. The semiconductor structure of claim 1 wherein the common plate is elongated horizontally.
9. The semiconductor structure of claim 1 wherein the common plate is elongated horizontally and vertically.
10. An array of capacitors, the capacitors within the array individually comprising:
a first capacitor electrode over a substrate;
a vertically-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being directly against a lateral side of the first capacitor electrode; and
a second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being directly against the other laterally-opposing side of the capacitor insulator, the second capacitor electrodes within the array being spaced longitudinally-elongated lines that are taller than they are wide and that extend horizontally along lines of the capacitors, individual of the second capacitor electrode lines being shared by capacitors longitudinally along that line of capacitors, the second capacitor electrode lines being longitudinally longer along that line of capacitors than are individual of the first capacitor electrodes longitudinally along that line of capacitors.
11. An array of memory cells individually comprising a capacitor and a transistor, the array comprising rows of access lines and columns of data/sense lines, comprising:
individual of the columns comprising a data/sense line electrically coupled with one source/drain region of individual transistors of individual memory cells within the array and interconnecting the transistors in that column;
individual of the rows comprising an access line above the data/sense lines, the access line extending operatively adjacent transistor channels and interconnecting the transistors in that row; and
capacitors of the individual memory cells within the array individually comprising:
a first capacitor electrode electrically coupled to and extending vertically upward from another source/drain region of one of the individual transistors;
a vertically-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being directly against a lateral side of the first capacitor electrode; and
a second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being directly against the other laterally-opposing side of the capacitor insulator, the second capacitor electrodes within the array being spaced longitudinally-elongated lines that are taller than they are wide and that extend horizontally along lines of the capacitors, individual of the second capacitor electrode lines being shared by capacitors longitudinally along that line of capacitors.
12. The array of claim 11 wherein at least a majority of the one laterally-opposing side of the capacitor insulator and the lateral side of the first capacitor electrode from top to bottom where such are directly against one another are each linearly straight in horizontal cross-section.
13. The array of claim 12 wherein all of the one laterally-opposing side of the capacitor insulator and the lateral side of the first capacitor electrode from top to bottom where such are directly against one another are each linearly straight form side-to-side in horizontal cross-section.
14. The array of claim 11 wherein at least a majority of the other laterally-opposing side of the capacitor insulator and the one laterally opposing side of the second capacitor electrode from top to bottom where such are directly against one another are each linearly straight in horizontal cross-section.
15. The array of claim 14 wherein all of the other laterally-opposing side of the capacitor insulator and the one laterally opposing side of the second capacitor electrode from top to bottom where such are directly against one another are each linearly straight in horizontal cross-section.
16. The array of claim 11 wherein the first capacitor electrodes individually from top to bottom are laterally-thinnest at the bottom.
17. The array of claim 11 wherein the first capacitor electrode is directly against an uppermost surface of the upper source/drain region, the first capacitor electrode being directly against less than all of the upper source/drain region uppermost surface.
18. The array of claim 17 wherein the first capacitor electrode is directly against no more than half of all of the upper source/drain region uppermost surface.
19. The array of claim 11 wherein the memory cells within a tier of the memory cells have translational symmetry where individual of the memory cells are 1T-1C and occupy a horizontal area of 2F 2 , where “F” is memory cell pitch taken horizontally, laterally, and orthogonally through individual of the second capacitor electrode lines, the capacitor insulator, and the first capacitor electrodes.
20. The array of claim 19 wherein the horizontal area is horizontally bounded by a 1F by 2F rectangle.
21. An array of memory cells individually comprising a capacitor and a transistor, the array comprising rows of access lines and columns of data/sense lines, comprising:
individual of the columns comprising a data/sense line electrically coupled with one source/drain region of individual transistors of individual memory cells within the array and interconnecting the transistors in that column;
individual of the rows comprising an access line above the data/sense lines, the access line extending operatively adjacent the transistor channels and interconnecting the transistors in that row; and
capacitors of the individual memory cells within the array individually comprising:
a first capacitor electrode electrically coupled to and extending vertically upward from another source/drain region of one of the individual transistors, the first capacitor electrodes individually from top to bottom are laterally-thinnest at the bottom;
a vertically-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being directly against a lateral side of the first capacitor electrode; and
a second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being directly against the other laterally-opposing side of the capacitor insulator, the second capacitor electrode being taller than it is wide.
22. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of access lines and columns of data/sense lines, comprising:
individual of the columns comprising a data/sense line under channels of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;
individual of the rows comprising an access line above the data/sense lines, the access line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and
capacitors of the individual memory cells within the array individually comprising:
a first capacitor electrode directly against and extending vertically upward from an uppermost surface of an upper source/drain region of one of the transistors, the first capacitor electrode being directly against less than all of the uppermost surface of the upper source/drain region;
a vertically-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being directly against a lateral side of the first capacitor electrode; and
a second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being directly against the other laterally-opposing side of the capacitor insulator, the second capacitor electrode being taller than it is wide.
23. The array of claim 22 wherein the first capacitor electrode is directly against no more than half of all of the upper source/drain region uppermost surface.