IP Library Granted Patent US 11,114,112
Granted Patent B2
US 11,114,112 · App. 16/428,778 · Granted Sep 7, 2021

Low power, high bandwidth, low latency data bus

Inventor: Jens Kristian Poulsen (Kitchener, CA)
Assignee: Google LLC
G10L21/055G06F3/162
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Quick Facts
Patent No.
US 11,114,112
App. No.
16/428,778
Granted
Sep 7, 2021
Kind
B2
Abstract

Data bus includes a device controller coupled to a first interface for digital communications using a first communications protocol, the device controller including a master bus controller controlling a multi-drop bus using a second communications protocol, and a slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the device controller using the second communications protocol. Each transmission line end is terminated using a device attached at one end of the transmission line and by another device attached at the other end. The second communications protocol supports multiple data rates using a fixed frame format. Safe synchronization may be established by systematically eliminating all false positions instead of searching for a valid candidate. Noise in the audio band may be lowered by scrambling of the data using a pseudo-random generator.

Claims (23)

1. A system comprising:

a master device coupled to a multi-drop bus for digital communications using a communications protocol comprising a plurality time slots; and

a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device in accordance with the communications protocol;

wherein at least one of the time slots is used to define a communications configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity;

wherein intermediate nodes on the multi-drop bus are connected to the multi-drop bus with short interruption to a travelling wave; and

wherein a physical length of disruptions to the transmission line resulting from intermediate nodes are shorter than the shortest wavelength used for signaling.

2. A system comprising:

a master device coupled to a multi-drop bus for digital communications comprising audio data and control signals using a communications protocol comprising a plurality time slots; and

a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device over the multi-drop bus in accordance with the communications protocol;

wherein at least one of the time slots is used to define a communications configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity, and

wherein delays between devices are measured by charging the bus to a known value, disabling drivers at a beginning and an end of the bus to cause the bus to be floating and not terminated during measurement, waiting for the devices to change a level on the bus, and measuring a transition delay.

3. A system comprising:

a master device coupled to a multi-drop bus for digital communications comprising audio data and control signals using a communications protocol comprising a plurality time slots; and

a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device over the multi-drop bus in accordance with the communications protocol;

wherein at least one of the time slots is used to define a communications configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity, and

wherein the system timing is obtained from a fractional phase locked loop (PLL) disposed in the master device and/or the first slave device and the PLL is dithered by adding an output from a pseudorandom generator to a fractional adder thereby reducing electromagnetic interference.

4. The system of claim 3 , wherein the PLL is configured to obtain lock between the master device and the first slave device.

5. The system of claim 4 , wherein the PLL includes a time-gate that is enabled during initial locking of the PLL and later only allows synchronization information to pass through to avoid the PLL to lock onto random bus traffic.

6. A system comprising:

a master device coupled to a multi-drop bus for digital communications comprising audio data and control signals using a communications protocol comprising a plurality time slots; and

a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device over the multi-drop bus in accordance with the communications protocol;

wherein at least one of the time slots is used to define a communications configuration for the first slave device to dynamically optimize bandwidth and/or signal integrity, and

wherein a pseudorandom generator is configured to scramble an output of one or more data ports thereby enabling a lower electromagnetic interference by whitening an output spectrum.

Assignments (4)
RELEASE OF PATENT SECURITY INTEREST Recorded May 6, 2021
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: SYNAPTICS INCORPORATED
Reel/Frame 056156/0797 →
CONFIRMATORY ASSIGNMENT Recorded Apr 30, 2021
From: SYNAPTICS INCORPORATED
To: GOOGLE LLC
Reel/Frame 056103/0543 →
SECURITY INTEREST Recorded Feb 14, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051936/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2019
From: POULSEN, JENS KRISTIAN
To: SYNAPTICS INCORPORATED
Reel/Frame 049977/0378 →