Conductive metal oxide structures in non-volatile re-writable memory devices
A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
1. An integrated circuit comprising:
a base layer comprising a plurality of active memory access circuits; and
a first memory layer formed above the base layer, the first memory layer comprising a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell, and wherein a plurality of memory cells in the first memory layer share one or more continuous and unetched layers of material disposed between the one of the plurality of row conductors and the one of the plurality of column conductors.
2. The integrated circuit of claim 1 , wherein the one or more continuous and unetched layers of material comprise:
an electrolytic insulator layer; and
a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer, wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power.
3. The integrated circuit of claim 2 , wherein a first portion of the conductive metal oxide layer associated with one of the plurality of memory cells has a crystalline structure and is electrically conductive, and wherein a second portion of the conductive metal oxide layer not associated with one of the plurality of memory cells has an amorphous structure and is electrically insulating.
4. The integrated circuit of claim 1 , further comprising:
a plurality of additional memory layers formed above the base layer, each of the additional memory layers comprising a separate cross-point memory array, wherein a plurality of memory cells in each of the additional memory layers share one or more continuous and unetched layers of material.
5. The integrated circuit of claim 4 , wherein each of the plurality of additional memory layers are electrically isolated from adjacent layers by a dielectric material.
6. The integrated circuit of claim 5 , wherein memory cells in adjacent layers of the plurality of additional memory layers share at least one of the plurality of row conductors or the plurality of column conductors.
7. The integrated circuit of claim 1 , wherein the base layer comprises a bulk silicon semiconductor substrate upon which the plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the first memory layer.
8. A memory device comprising:
a base layer comprising a plurality of active memory access circuits; and
a plurality of memory layers formed above the base layer, each of the memory layers comprising a separate cross-point memory array, each cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell, and wherein a plurality of memory cells in each of the memory layers share one or more separate continuous and unetched layers of material.
9. The memory device of claim 8 , wherein the one or more separate continuous and unetched layers of material each comprise:
an electrolytic insulator layer; and
a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer, wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power.
10. The memory device of claim 9 , wherein a first portion of the conductive metal oxide layer associated with one of the plurality of memory cells has a crystalline structure and is electrically conductive, and wherein a second portion of the conductive metal oxide layer not associated with one of the plurality of memory cells has an amorphous structure and is electrically insulating.
11. The memory device of claim 8 , wherein each of the plurality of memory layers are electrically isolated from adjacent layers by a dielectric material.
12. The memory device of claim 11 , wherein memory cells in adjacent layers of the plurality of memory layers share at least one of the plurality of row conductors or the plurality of column conductors.
13. The memory device of claim 8 , wherein the base layer comprises a bulk silicon semiconductor substrate upon which the plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the plurality of memory layers.
14. A system comprising:
a processing device; and
a memory device coupled to the processing device, wherein the memory device comprises:
a base layer comprising a plurality of active memory access circuits; and
a first memory layer formed above the base layer, the first memory layer comprising a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell, and wherein a plurality of memory cells in the first memory layer share one or more continuous and unetched layers of material disposed between the one of the plurality of row conductors and the one of the plurality of column conductors.
15. The system of claim 14 , wherein the one or more continuous and unetched layers of material comprise:
an electrolytic insulator layer; and
a conductive metal oxide layer in contact with the electrolytic insulator layer and configured to be reversibly programmable between multiple resistance states via exchange of mobile ions with the electrolytic insulator layer, wherein the electrolytic insulator layer and the conductive oxide layer are configured to store at least one bit of data as a plurality of conductivity profiles that are retained in an absence of electrical power.
16. The system of claim 15 , wherein a first portion of the conductive metal oxide layer associated with one of the plurality of memory cells has a crystalline structure and is electrically conductive, and wherein a second portion of the conductive metal oxide layer not associated with one of the plurality of memory cells has an amorphous structure and is electrically insulating.
17. The system of claim 14 , wherein the memory device further comprises:
a plurality of additional memory layers formed above the base layer, each of the additional memory layers comprising a separate cross-point memory array, wherein a plurality of memory cells in each of the additional memory layers share one or more continuous and unetched layers of material.
18. The system of claim 17 , wherein each of the plurality of additional memory layers are electrically isolated from adjacent layers by a dielectric material.
19. The system of claim 18 , wherein memory cells in adjacent layers of the plurality of additional memory layers share at least one of the plurality of row conductors or the plurality of column conductors.
20. The system of claim 14 , wherein the base layer comprises a bulk silicon semiconductor substrate upon which the plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the first memory layer.