IP Library Patent Application 16429660
Patent Application
App. No. 16/429,660

ELECTRICAL LINE STATUS MONITORING SYSTEM

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Patent No.
US None
App. No.
16/429,660
Abstract

Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system.

Claims (36)

1 - 20 . (canceled)

21 . An apparatus for detecting a status of a circuit, the apparatus comprising:

a first node and a second node, coupled to the circuit;

a voltage generator configured to generate an output voltage to the circuit via the second node;

a current source, coupled to the circuit via the first node, to provide a current to the circuit via the first node to generate a first node voltage at the first node; and

a first comparator, coupled to the first node, to generate a first comparison result according to the first node voltage and a reference voltage;

wherein the first comparison result indicates whether the status of at least one of a plurality of circuit elements is short or not.

22 . The apparatus of claim 21 , wherein the circuit further comprises a first device, coupled between the circuit elements and the current source, wherein the first device receives a control voltage and the first device is on or off status according to the control voltage.

23 . The apparatus of claim 22 , wherein the circuit further comprises a first voltage divider, coupled to the second node and the first device, to generate the control voltage.

24 . The apparatus of claim 21 , wherein the circuit further comprises a transistor which operates in a linear region.

25 . The apparatus of claim 21 , further comprising:

a third node, coupled to a second circuit, wherein the second circuit comprises a plurality of second diodes; and

a second comparator, coupled to the third node, to generate a second comparison result according to a voltage at the third node and the reference voltage.

26 . The apparatus of claim 21 , the voltage generator comprising a first transistor and a second transistor, wherein the first transistor is coupled between the second transistor and the second node.

27 . The apparatus of claim 26 , wherein the first transistor and the second transistor are coupled in series.

28 . The apparatus of claim 21 , the voltage generator comprising:

a first transistor and a second transistor, wherein the first transistor is coupled between the second transistor and the second node; and

a plurality of diodes coupled in series, wherein one of the diodes is coupled to the second node.

29 . The apparatus of claim 28 , wherein the first transistor and the second transistor are coupled in series.

30 . The apparatus of claim 28 , further comprising a third transistor.

31 . The apparatus of claim 21 , further comprising a control circuit having a plurality of operation modes, wherein the control circuit switches to perform a corresponding operation mode.

32 . The apparatus of claim 31 , wherein the control circuit controls a first switch of the plurality of switches such that the voltage generator is coupled to the second node.

33 . The apparatus of claim 32 , wherein the apparatus further comprises a second voltage divider coupled between an input of the first comparator and the first node, wherein the control circuit controls a third switch of the plurality of switches to allow the second voltage divider to divide the first node voltage.

34 . The apparatus of claim 31 , wherein the control circuit controls the plurality of switches such that an internal circuit is coupled to the second node, and the voltage generator is not coupled to the second node.

35 . A method for detecting a status, the method comprising:

providing a first current to a circuit via a first node;

providing a control voltage to a control input to generate a first node voltage at the first node according to the first current; and

generating a first comparison result according to the first node voltage and a reference voltage, wherein the first comparison result indicates whether the status of at least one of a series of components is short.

36 . The method of claim 35 , further comprising controlling a first switch of a plurality of switches such that an output voltage is provided to the circuit in a detecting mode.

37 . The method of claim 35 , further comprising coupling the second node to an internal circuit.

38 . In an apparatus for detecting a status of a circuit, the apparatus having a first node and a second node, coupled to the circuit, a voltage generator configured to generate an output voltage to the circuit via the second node, a current source, coupled to the circuit via the first node, to provide a current to the circuit via the first node to generate a first node voltage at the first node, a first comparator, coupled to the first node, to generate a first comparison result according to the first node voltage and a reference voltage, wherein the first comparison result indicates whether the status of at least one of a plurality of circuit elements is short or not, wherein the circuit further includes a first device, coupled between the circuit elements and the current source, wherein the first device receives a control voltage and the first device is on or off status according to the control voltage, wherein the circuit further comprises a first voltage divider, coupled to the second node and the first device, to generate the control voltage, wherein the circuit further comprises a transistor which operates in a linear region, a third node, coupled to a second circuit, wherein the second circuit comprises a plurality of second diodes, a second comparator, coupled to the third node, to generate a second comparison result according to a voltage at the third node and the reference voltage, the voltage generator comprising a first transistor and a second transistor, wherein the first transistor is coupled between the second transistor and the second node, wherein the first transistor and the second transistor are coupled in series, a plurality of diodes coupled in series, wherein one of the diodes is coupled to the second node, a third transistor, a control circuit having a plurality of operation modes, wherein the control circuit switches to perform a corresponding operation mode, wherein the control circuit controls a first switch of the plurality of switches such that the voltage generator is coupled to the second node, wherein the apparatus further comprises a second voltage divider coupled between an input of the first comparator and the first node, wherein the control circuit controls a third switch of the plurality of switches to allow the second voltage divider to divide the first node voltage, wherein the control circuit controls the plurality of switches such that an internal circuit is coupled to the second node, and the voltage generator is not coupled to the second node, a method comprising:

providing a first current to a circuit via a first node;

providing a control voltage to a control input to generate a first node voltage at the first node according to the first current;

generating a first comparison result according to the first node voltage and a reference voltage, wherein the first comparison result indicates whether the status of at least one of a series of components is short;

controlling a first switch of a plurality of switches such that an output voltage is provided to the circuit in a detecting mode; and

coupling the second node to an internal circuit.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (050437/0902) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062784/0069 →
SECURITY INTEREST Recorded Sep 19, 2019
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 050437/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2019
From: TEGGATZ, ROSS E.; CHEN, WAYNE; SMITH, BRETT; KOHOUT, JAMES
To: TRIUNE SYSTEMS, LLC
Reel/Frame 049348/0737 →