Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising:

a cell unit including:

a first selection gate transistor,

a second selection gate transistor, and

a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor; and

a data write circuit configured to execute a writing operation to write data to the memory cells;

wherein

the memory cells include:

a first memory cell connected with a first word line and capable of being programmable in D 1 stages to thereby store data of D 1 bits, D 1 being an integer of 1 or more,

a second memory cell connected with a second word line and capable of being programmable in D 2 stages to thereby store data of D 2 bits, D 2 being an integer of 3 or more and greater than D 1 , the second memory cell being closer to the first selection gate transistor than the first memory cell,

a third memory cell connected with a third word line and capable of being programmable in D 3 stages to thereby store data of D 3 bits, D 3 being an integer of 3 or more and greater than D 1 , the third memory cell being closer to the first selection gate transistor than the second memory cell, and

a fourth memory cell connected with a fourth word line and capable of being programmable in D 4 stages to thereby store data of D 4 bits, D 4 being an integer of 3 or more and greater than D 1 , the fourth memory cell being closer to the first selection gate transistor than the third memory cell; and

the data write circuit executes:

a first program on the third memory cell as a first one of the D 3 stages,

a second program on the fourth memory cell as a second or higher one of the D 4 stages, after the first program,

a third program on the second memory cell as a first one of the D 2 stages, after the second program,

a fourth program on the third memory cell as a second or higher one of the D 3 stages, after the third program,

a fifth program on the first memory cell as a first one of the D 1 stages, after the fourth program, and

a sixth program on the second memory cell as a second or higher one of the D 2 stages, after the fifth program.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein

the sixth program on the second memory cell is performed as the second one of the D 2 stages, and

the data write circuit further executes

a seventh program on the second memory cell as a third or higher one of the D 2 stages, after the sixth program.

3. The nonvolatile semiconductor memory device according to claim 2 , wherein

the second program on the fourth memory cell is performed as the second one of the D 4 stages,

the fourth program on the third memory cell is performed as the second one of the D 3 stages, and

the data write circuit further executes

an eighth program on the fourth memory cell as a third or higher one of the D 4 stages, after the third program and before the fifth program, and

a ninth program on the third memory cell as a third or higher one of the D 3 stages, after the fifth program and before the seventh program.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein

D 1 is 1,

D 2 is 3,

D 3 is 3, and

D 4 is 3.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein

the cell unit further includes:

a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and

a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

6. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a source line connected to a source of the first selection gate transistor; and

a bit line connected to a drain of the second selection gate transistor.

7. A nonvolatile semiconductor memory device, comprising:

a cell unit including:

a first selection gate transistor,

a second selection gate transistor, and

a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor, and

a data write circuit configured to execute a writing operation to write data to the memory cells;

wherein

the memory cells include:

a first memory cell connected with a first word line and capable of being programmable in D 1 stages to thereby store data of D 1 bits, D 1 being an integer of 1 or more,

a second memory cell connected with a second word line and capable of being programmable in D 2 stages to thereby store data of D 2 bits, D 2 being an integer of 3 or more and greater than D 1 , the second memory cell being closer to the first selection gate transistor than the first memory cell,

a third memory cell connected with a third word line and capable of being programmable in D 3 stages to thereby store data of D 3 bits, D 3 being an integer of 3 or more and greater than D 1 , the third memory cell being closer to the first selection gate transistor than the second memory cell, and

a fourth memory cell connected with a fourth word line and capable of being programmable in D 4 stages to thereby store data of D 4 bits, D 4 being an integer of 3 or more and greater than D 1 , the fourth memory cell being closer to the first selection gate transistor than the third memory cell; and

the data write circuit executes:

a first program on the third memory cell as a second or lower one of the D 3 stages,

a second program on the fourth memory cell as a final one of the D 4 stages, after the first program,

a third program on the second memory cell as a second or lower one of the D 2 stages, after the second program,

a fourth program on the third memory cell as a final one of the D 3 stages, after the third program,

a fifth program on the first memory cell as a first or higher one of the D 1 stages, after the fourth program, and

a sixth program on the second memory cell as a final one of the D 2 stages, after the fifth program.

8. The nonvolatile semiconductor memory device according to claim 7 , wherein

the third program on the second memory cell is performed as the second one of the D 2 stages, and

the data write circuit further executes

a seventh program on the second memory cell as a first one of the D 2 stages, before the first program.

9. The nonvolatile semiconductor memory device according to claim 8 , wherein

the first program on the third memory cell is performed as the second one of the D 3 stages, and

the data write circuit further executes

an eighth program on the third memory cell as a first one of the D 4 stages, before the seventh program.

10. The nonvolatile semiconductor memory device according to claim 7 , wherein

D 1 is 1,

D 2 is 3,

D 3 is 3, and

D 4 is 3.

11. The nonvolatile semiconductor memory device according to claim 7 , wherein

the cell unit further includes:

a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and

a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

12. The nonvolatile semiconductor memory device according to claim 7 , further comprising:

a source line connected to a source of the first selection gate transistor; and

a bit line connected to a drain of the second selection gate transistor.