IP Library Granted Patent US 10,498,313
Granted Patent B1
US 10,498,313 · App. 16/432,329 · Granted Dec 3, 2019

Level shift circuit

Inventors: Kosuke Takada (Chiba, JP); Masayuki Uno (Chiba, JP)
Assignee: ABLIC INC.
H03K3/037H03K19/018521
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Quick Facts
Patent No.
US 10,498,313
App. No.
16/432,329
Granted
Dec 3, 2019
Kind
B1
Abstract

A level shift circuit includes two resistors by which logic is fixed when two input terminals become low level, and a logic circuit and transistors which set the logic of an output terminal to a desired value according to the fixation of the logic.

Claims (15)

1. A level shift circuit comprising:

a first transistor having a source connected to a first power supply terminal;

a second transistor having a source connected to the first power supply terminal, a gate connected to a drain of the first transistor, and a drain connected to a gate of the first transistor;

a first resistive element connected between the first power supply terminal and the drain of the first transistor;

a second resistive element connected between the first power supply terminal and the drain of the second transistor;

a third transistor having a source connected to a second power supply terminal, a gate connected to a first input terminal, and a drain connected to the drain of the first transistor;

a fourth transistor having a source connected to the second power supply terminal, a gate connected to a second input terminal, and a drain connected to the drain of the second transistor;

a fifth transistor having a source connected to the first power supply terminal, a gate connected to the drain of the second transistor, and a drain connected to an output terminal of the level shift circuit;

a logic circuit having a first input terminal connected to the drain of the first transistor, and a second input terminal connected to the drain of the second transistor; and

a sixth transistor having a source connected to the first power supply terminal, a gate connected to an output terminal of the logic circuit, and a drain connected to the output terminal of the level shift circuit.

2. The level shift circuit according to claim 1 , wherein the logic circuit turns on the sixth transistor when voltages of the first and second input terminals are equal to a voltage of the first power supply terminal.

3. The level shift circuit according to claim 1 , further comprising:

a constant voltage circuit having one end connected to the first power supply terminal;

a seventh transistor having a gate connected to the other end of the constant voltage circuit and connected between the drain of the first transistor and the drain of the third transistor; and

an eighth transistor having a gate connected to the other end of the constant voltage circuit and connected between the drain of the second transistor and the drain of the fourth transistor.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2019
From: TAKADA, KOSUKE; UNO, MASAYUKI
To: ABLIC INC.
Reel/Frame 049383/0321 →