Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
View Patent ↗Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
1. A memory device, comprising:
a first memory portion;
a second memory portion;
a mode register; and
circuitry configured, in response to receiving a command to perform a refresh operation at the first memory portion, to:
perform the refresh operation at the first memory portion,
perform a read of the mode register, and
provide on-die termination at the second memory portion during at least a portion of the read of the mode register.
2. The memory device of claim 1 , wherein the read of the mode register includes outputting data from the mode register from the memory device.
3. The memory device of claim 2 , wherein the outputted data includes information corresponding to a temperature of the first memory portion.
4. The memory device of claim 2 , wherein the outputted data includes information corresponding to a refresh rate of the first memory portion.
5. The memory device of claim 1 , wherein the command has a duration on a command/address bus of the memory device of a single clock cycle of the memory device.
6. The memory device of claim 1 , wherein the mode register corresponds to the first memory portion.
7. A method of operating a memory system, comprising:
receiving a command instructing a first portion of the memory system to perform a refresh operation;
in response to the command,
performing the refresh operation at the first portion of the memory system,
performing a read of a mode register of the memory system, and
providing on-die termination at a second portion of the memory system during at least a portion of the read of the mode register.
8. The method of claim 7 , wherein the read of the mode register includes outputting data from the mode register from the memory system.
9. The method of claim 8 , wherein the outputted data includes information corresponding to a temperature of the first portion.
10. The method of claim 8 , wherein the outputted data includes information corresponding to a refresh rate of the first portion.
11. The method of claim 7 , wherein the command has a duration on a command/address bus of the memory system of a single clock cycle of the memory system.
12. The method of claim 7 , further comprising:
receiving at least a first chip select signal indicating which of the first and second portions are to perform the refresh operation.
13. The method of claim 7 , further comprising:
receiving at least a first enable signal indicating that the second portion is to provide the on-die termination.
14. A method of operating a memory system, comprising:
sending a command instructing a first portion of the memory system to perform a refresh operation;
in response to the command to perform a refresh operation, receiving data output from a mode register of the memory system while a second portion of the memory system provides on-die termination.
15. The method of claim 14 , wherein the outputted data includes information corresponding to a temperature and/or a refresh rate of the first portion.