Field programmable gate array including coupled lookup tables

1. A field programmable logic device comprising:

a first logic block comprising a first lookup table; and

a second logic block comprising a second lookup table, wherein the first logic block is directly coupled to the second logic block,

wherein the first lookup table comprises a plurality of first memory cells, the second lookup table comprises a plurality of second memory cells, each first memory cell of the first lookup table is directly coupled to a corresponding second memory cell of the second lookup table,

wherein the first logic block is configured to pass, upon a clock cycle of the field programmable logic device, data about a lookup table configuration stored in the plurality of first memory cells of the first lookup table to the plurality of memory cells of the second lookup table, respectively, and

wherein the plurality of first memory cells and the plurality of second memory cells comprise D-type flip-flop registers.

2. The field programmable logic device of claim 1 , wherein, for each first memory cell of the first lookup table coupled to a corresponding second memory cell of the second lookup table, a data output of the first memory cell is coupled to a data input of the second memory cell.

3. The field programmable logic device of claim 1 , wherein each first memory cell of the first lookup table and each second memory cell of the second lookup table comprises a corresponding clock input terminal tied to a same clock signal source.

4. The field programmable logic device of claim 1 , wherein the first lookup table of the first logic block is configured to receive a lookup table configuration from a read-only memory component.

5. A method of updating a lookup table configuration across logic blocks of a field programmable logic device, the method comprising:

receiving, at a first logic block of the field programmable logic device, a clock pulse;

upon receiving the clock pulse, receiving at a first lookup table of the first logic block, a first lookup table configuration;

upon receiving the clock pulse, transmitting from the first lookup table, directly to a second lookup table of a second logic block of the field programmable logic device, a second lookup table configuration; and

storing the first lookup table configuration in the first lookup table of the first logic block,

wherein the second lookup table configuration is transmitted to the second logic block before the first lookup table configuration is stored in the first logic block,

wherein the first lookup table comprises a plurality of first memory cells, the second lookup table comprises a plurality of second memory cells, each first memory cell of the first lookup table is directly coupled to a corresponding memory cell of the second lookup table, and

wherein the plurality of first memory cells and the plurality of second memory cells comprise D-type flip-flop registers.

6. The method of claim 5 , wherein, prior to the first lookup table configuration being received at the first lookup table of the first logic block, the first lookup table configuration is stored in a third lookup table of a third logic block.

7. The method of claim 5 , wherein, for each first memory cell of the first lookup table coupled to a corresponding second memory cell of the second lookup table, a data output of the first memory cell is coupled to a data input of the second memory cell.

8. The method of claim 5 , wherein each first memory cell of the first lookup table and each second memory cell of the second lookup table comprises a corresponding clock input terminal tied to a same clock signal source.

9. The method of claim 5 , wherein the first lookup table of the first logic block is configured to receive the first lookup table configuration from a read-only memory component.

10. The method of claim 5 , wherein the first lookup table configuration is shifted into the second lookup table of the second logic block one bit at each cycle of a clock cycle.