Semiconductor solid state battery
A semiconductor solid state battery has an insulating layer provided between an N-type semiconductor and a P-type semiconductor. The first insulating layer preferably has a thickness of 3 nm to 30 μm and a dielectric constant of 10 or less. The first insulating layer preferably has a density of 60% or more of a bulk body. The semiconductor layer preferably has a capture level introduced. The semiconductor solid state battery can eliminate leakage of an electrolyte solution.
1. A semiconductor solid state battery comprising:
an N-type semiconductor;
a P-type semiconductor; and
a first insulating layer provided between the N-type semiconductor and the P-type semiconductor,
wherein the first insulating layer has a thickness of 3 nm to 30 μm and a dielectric constant of 50 or less.
2. The semiconductor solid state battery according to claim 1 , wherein the first insulating layer has a dielectric constant of 10 or less.
3. The semiconductor solid state battery according to claim 1 , wherein the first insulating layer has a density of 60% or more of a true density thereof.
4. The semiconductor solid state battery according to claim 1 , wherein at least one of the N-type semiconductor and the P-type semiconductor is made of one selected from the group consisting of metal silicide, metal oxide, amorphous silicon, crystalline silicon, polycrystalline silicon, and monocrystalline silicon.
5. The semiconductor solid state battery according to claim 4 , wherein the N-type semiconductor or the P-type semiconductor comprises capture levels for electrons or holes in a range of 10 17 cm −3 to 10 22 cm −3 introduced therein.
6. The semiconductor solid state battery according to claim 1 , wherein the N-type semiconductor or the P-type semiconductor comprises a capture level for electrons or holes introduced therein.
7. The semiconductor solid state battery according to claim 6 , wherein the N-type semiconductor comprises the capture level for the electrons, the capture level being introduced in the range of 50 to 90 taking a band gap of the N-type semiconductor as 100.
8. The semiconductor solid state battery according to claim 7 , wherein the N-type semiconductor comprises the capture level for the electrons in a range of 10 17 cm −3 to 10 22 cm −3 .
9. The semiconductor solid state battery according to claim 6 , wherein the P-type semiconductor comprises the capture level for the holes, the capture level being introduced in the range of 10 to 50 taking a band gap of the P-type semiconductor as 100.
10. The semiconductor solid state battery according to claim 9 , wherein the P-type semiconductor comprises the capture level for the holes in a range of 10 17 cm −3 to 10 22 cm −3 .
11. The semiconductor solid state battery according to claim 1 , further comprising a first electrode provided on the N-type semiconductor and a second electrode provided on the P-type semiconductor.
12. The semiconductor solid state battery according to claim 11 , further comprising a second insulating layer provided between the N-type semiconductor and the first electrode,
a third insulating layer provided between the P-type semiconductor and the second electrode, or
both the second insulating layer and the third insulating layer.
13. The semiconductor solid state battery according to claim 12 , wherein at least one of the second insulating layer and the third insulating layer has a thickness of 30 nm or less and a dielectric constant of 50 or less.
14. The semiconductor solid state battery according to claim 13 , wherein at least one of the second insulating layer and the third insulating layer has a dielectric constant of 10 or less.
15. The semiconductor solid state battery according to claim 1 , wherein the N-type semiconductor or the P-type semiconductor comprises capture levels for electrons or holes in a range of 10 17 cm −3 to 10 22 cm −3 introduced therein.
16. A semiconductor solid state battery comprising:
an N-type semiconductor;
a P-type semiconductor; and
a first insulating layer provided between the N-type semiconductor and the P-type semiconductor, the N-type semiconductor or the P-type semiconductor comprising a capture level for electrons or holes introduced therein.
17. The semiconductor solid state battery according to claim 16 , wherein the N-type semiconductor or the P-type semiconductor comprises the capture levels in a range of 10 17 cm −3 to 10 22 cm −3 .
18. A semiconductor solid state battery comprising:
an N-type semiconductor;
a P-type semiconductor;
a first insulating layer provided between the N-type semiconductor and the P-type semiconductor;
a first electrode provided on the N-type semiconductor;
a second electrode provided on the P-type semiconductor; and
a second insulating layer provided between the N-type semiconductor and the first electrode, a third insulating layer provided between the P-type semiconductor and the second electrode, or both the second insulating layer and the third insulating layer.
19. The semiconductor solid state battery according to claim 18 , wherein at least one of the second insulating layer and the third insulating layer has a thickness of 30 nm or less and a dielectric constant of 50 or less.
20. The semiconductor solid state battery according to claim 19 , wherein at least one of the second insulating layer and the third insulating layer has a dielectric constant of 10 or less.