Excess loop delay estimation and correction

1. A system comprising:

an analog-to-digital conversion circuit comprising a loop filter circuit, an analog-to-digital converter (ADC), a noise transfer function impulse response detection circuitry, a random sequence generation circuit, and loop filter configuration circuitry wherein:

an output of the loop filter circuit is converted to a digital signal by the ADC;

a random sequence generated by the random sequence generation circuit is added to the digital signal to generate a randomized digital signal;

the noise transfer function impulse response detection circuitry is configured to process the randomized digital signal and the random sequence to determine a noise transfer function impulse response; and

the loop filter configuration circuitry is operable to configure the loop filter circuit based on the noise transfer function impulse response.

2. The system of claim 1 , wherein the random sequence generation circuit comprises a high-pass sigma delta modulator.

3. The system of claim 1 , wherein the loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response determined by the noise transfer function impulse response detection circuitry.

4. The system of claim 3 , wherein the loop filter configuration circuitry is operable to generate loop filter coefficients based on the noise transfer function impulse response.

5. The system of claim 1 , comprising a digital-to-analog converter circuit (DAC), wherein the randomized digital signal is fed back to the loop filter circuit via the DAC.

6. The system of claim 1 , comprising a noise compensation circuit operable to:

generate a compensation signal by filtering the random sequence based on the noise transfer function impulse response; and

subtract the compensation signal from the randomized digital signal to generate a compensated, randomized digital signal.

7. The system of claim 6 , comprising a digital-to-analog converter circuit (DAC), wherein the compensated, randomized digital signal is fed back to the loop filter circuit via the DAC.

8. The system of claim 1 , wherein the noise transfer function impulse response detection circuitry is operable to determine a correlation between the random sequence and the randomized digital signal.

9. The system of claim 1 , wherein, for each value of the random sequence, the addition of the random sequence to the digital signal corresponds to addition or subtraction of a value equal to 1 least significant bit of the ADC.

10. The system of claim 1 , wherein the loop filter circuit comprises excess loop delay compensation circuitry which reuses a last integrator operational amplifier of the loop filter circuit to provide direct path addition.

11. The system of claim 10 , wherein:

a positive terminal of the output of the loop filter circuit is applied to a first input of the operational amplifier through a first resistor and to a second input of the operational amplifier through a second resistor and a first capacitor in series;

a negative terminal of the output of the loop filter circuit is applied to the first input of the operational amplifier through a third resistor and a second capacitor in series and to the second input of the operational amplifier through a fourth resistor.

12. A method comprising:

converting, by an analog-to-digital convertor circuit (ADC) an output of a loop filter circuit to a digital signal;

generating, by a random sequence generation circuit, a random sequence;

adding, by adder circuitry, the random sequence to the digital signal to generate a randomized digital signal;

processing, by noise transfer function impulse response detection circuitry, the randomized digital signal and the random sequence to determine a noise transfer function impulse response; and

configuring, by loop filter configuration circuitry, the loop filter circuit based on the noise transfer function impulse response.

13. The method of claim 12 , wherein the random sequence generation circuit comprises a high-pass sigma delta modulator.

14. The method of claim 12 , comprising:

determining, by the noise transfer function impulse response detection circuitry, the noise transfer function impulse response; and

configuring, by the loop filter configuration circuitry, the loop filter circuit based on the noise transfer function impulse response.

15. The method of claim 14 , comprising generating, by the loop filter configuration circuitry, loop filter coefficients based on the noise transfer function impulse response.

16. The method of claim 12 , comprising feeding the randomized digital signal back to the loop filter circuit via a digital-to-analog converter circuit (DAC).

17. The method of claim 12 , comprising:

generating, by noise compensation circuitry, a compensation signal by filtering the random sequence based on the noise transfer function impulse response; and

subtracting the compensation signal from the randomized digital signal to generate a compensated, randomized digital signal.

18. The method of claim 17 , comprising feeding the compensated, randomized digital signal to the loop filter circuit via a digital-to-analog converter circuit (DAC).

19. The method of claim 12 , comprising determining, by the noise transfer function impulse response detection circuitry, a correlation between the random sequence and the randomized digital signal.

20. The method of claim 12 , wherein, for each value of the random sequence, the addition of the random sequence to the digital signal corresponds to addition or subtraction of a value equal to 1 least significant bit of the ADC.