Semiconductor memory device and method for manufacturing same

1. A semiconductor memory device, comprising:

a stacked body including

a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of electrode layers alternately stacked with a plurality of insulating layers therebetween, and

an intermediate layer provided above the first stacked unit and below the second stacked unit, the intermediate layer being made of a material different from the electrode layers and the insulating layers;

a plurality of columnar members each piercing the stacked body and including a channel body extending in a stacking direction of the stacked body; and

an insulating member extending along the stacking direction from an upper end of the second stacked unit to a lower end of the first stacked unit, the insulating member and the columnar members being arranged in a first direction perpendicular to the stacking direction with the stacked body interposed, wherein

a stepped portion is formed in a first sidewall of the insulating member, the stepped portion being positioned at a height between the first stacked unit and the second stacked unit in the stacking direction.

2. The device according to claim 1 , wherein

a plurality of memory cells are provided at intersections between the channel body and the electrode layers.

3. The device according to claim 1 , wherein

the stepped portion is positioned at a height corresponding to the intermediate layer.

4. The device according to claim 1 , wherein

a width of the insulating member in the first direction is larger than a diameter of the channel body.

5. The device according to claim 1 , wherein

the stepped portion is formed in the first sidewall of the insulating member facing to the columnar members.

6. The device according to claim 1 , wherein

a stepped portion is further formed in a second sidewall of the insulating member other than the first sidewall at a height between the first stacked unit and the second stacked unit in the stacking direction.

7. The device according to claim 1 , wherein

the columnar members are arranged in a second direction crossing the first direction.

8. The device according to claim 1 , wherein

the electrode layers include silicon and the insulating layers include silicon oxide.

9. The device according to claim 1 , wherein

the insulating member includes silicon oxide.

10. The device according to claim 1 , wherein

the intermediate layer includes a metal element.

11. The device according to claim 1 , wherein

the electrode layers are provided around outer circumferential surfaces of the columnar members.

12. A semiconductor device comprising:

first memory cells provided in a first stacked body including first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body; and

second memory cells provided in a second stacked body including second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body, the first and second semiconductor portions being electrically connected with each other and being included in a columnar member extending in a stacking direction of the first and second stacked bodies;

an intermediate layer provided above the first stacked body and below the second stacked body, the intermediate layer being made of a material different from the first and second electrode layers and the first and second insulating layers; and

an insulating member extending along the stacking direction from an upper end of the second stacked body to a lower end of the first stacked body, the insulating member and the columnar member being arranged in a first direction perpendicular to the stacking direction with the first and second stacked bodies interposed, wherein

a stepped portion is formed in a first sidewall of the insulating member at a same level as the intermediate layer in the stacking direction.

13. The device according to claim 12 , wherein

a width of the insulating member in the first direction is larger than diameters of the first and second semiconductor portions.

14. The device according to claim 12 , wherein

the stepped portion is formed in the first sidewall of the insulating member facing to the columnar member.

15. The device according to claim 12 , wherein

a stepped portion is further formed in a second sidewall of the insulating member other than the first sidewall at the same level as the intermediate layer.

16. The device according to claim 12 , wherein

plural columnar members extending through the first and second stacked bodies are arranged in a second direction crossing the first direction.

17. The device according to claim 12 , wherein

the first and second electrode layers include silicon and the first and second insulating layers include silicon oxide.

18. The device according to claim 12 , wherein

the insulating member includes silicon oxide.

19. The device according to claim 12 , wherein

the intermediate layer includes a metal element.

20. The device according to claim 12 , wherein

the first and second electrode layers are provided around outer circumferential surfaces of the first and second semiconductor portions.