SELF-ALIGNED TRENCH METAL-ALLOYING FOR III-V NFETS
After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.
1 . A semiconductor structure comprising:
source/drain regions located on opposite sides of a gate structure that is located on a compound semiconductor channel layer;
an interlevel dielectric (ILD) located on the source/drain regions and laterally adjacent to the gate structure;
source/drain contact openings extending through the ILD layer, each of the source/drain contact openings exposing a portion of one of the source/drain regions;
metal semiconductor alloy regions located at bottom of the source/drain contact openings, each of the metal semiconductor alloy regions contacting a top surface of the exposed portion of one of the source/drain regions; and
source/drain contacts located within the source/drain contact openings, each of the source/drain contacts contacting a top surface of the metal semiconductor alloy regions.
2 . The semiconductor structure of claim 1 , wherein the compound semiconductor channel layer comprises a III-V compound semiconductor material.
3 . The semiconductor structure of claim 2 , wherein the compound semiconductor channel layer comprises GaAs, InAs, InP, InGaAs, InAlAs, InAlAsSb, InAlAsP or InGaAsP.
4 . The semiconductor structure of claim 1 , wherein the source/drain regions comprises planar source/drain regions located within the compound semiconductor channel layer.
5 . The semiconductor structure of claim 4 , wherein the source/drain regions further comprises raised source/drain regions having a same type of doping as the planar source/drain regions, wherein each of the raised source/drain region contacts a top surface of one of the planar source/drain regions.
6 . The semiconductor structure of claim 5 , wherein the raised source/drain regions comprise a same III-V compound semiconductor material as the planar source/drain regions.
7 . The semiconductor structure of claim 6 , wherein each of the raised source/drain regions and the planar source/drain regions comprises Si doped InGaAs.
8 . The semiconductor structure of claim 1 , further comprising a compound semiconductor substrate layer located beneath the compound semiconductor channel layer.
9 . The semiconductor structure of claim 8 , wherein the compound semiconductor substrate layer comprises InP, and the compound semiconductor channel layer comprises InGaAs.
10 . The semiconductor structure of claim 1 , wherein the source/drain contacts have a contact resistance that is lower than 5×10 −9 ohm-cm 2 .
11 . The semiconductor structure of claim 1 , wherein the top surface of each of the source/drain regions is essentially free of native oxides.
12 . The semiconductor structure of claim 1 , wherein each of source/drain regions comprises a III-V compound semiconductor that is doped with Si.
13 . The semiconductor structure of claim 1 , wherein each of source/drain regions comprises a III-V compound semiconductor that is doped with Ge.
14 . The semiconductor structure of claim 1 , wherein each of source/drain regions comprises a III-V compound semiconductor that is doped with Sn.
15 . The semiconductor structure of claim 1 , wherein each of source/drain regions comprises a III-V compound semiconductor that is doped with Te.
16 . The semiconductor structure of claim 1 , wherein the metal semiconductor alloy regions are composed of a silicide.
17 . The semiconductor structure of claim 1 , wherein the metal semiconductor alloy regions are composed of a gemicide.
18 . The semiconductor structure of claim 1 , wherein the metal semiconductor alloy regions are located completely beneath the source/drain contacts.
19 . The semiconductor structure of claim 1 , wherein the source/drain contacts have a topmost surface that is coplanar with a topmost surface of the ILD.
20 . The semiconductor structure of claim 1 , wherein the metal semiconductor alloy regions and the source/drain contacts have sidewalls that directly contact the ILD.