IP Library Granted Patent US 10,922,078
Granted Patent B2
US 10,922,078 · App. 16/444,577 · Granted Feb 16, 2021

Host processor configured with instruction set comprising resilient data move instructions

Inventors: Michael Robillard (Shrewsbury, MA); Adrian Michaud (Carlisle, MA); Dragan Savic (Brookline, MA)
Assignee: EMC IP Holding Company LLC
G06F9/30032G06F3/0604G06F3/0647G06F3/0673
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Quick Facts
Patent No.
US 10,922,078
App. No.
16/444,577
Granted
Feb 16, 2021
Kind
B2
Abstract

A system includes a host processor and at least one storage device coupled to the host processor. The host processor is configured to execute instructions of an instruction set, the instruction set comprising a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations. The host processor, in executing the first move instruction, is configured to store the data in a first one of the storage locations identified by one or more additional operands of the first move instruction, and to store the data in a second one of the storage locations identified based at least in part on the first storage location. The instruction set in some embodiments further comprises a second move instruction for moving the data from the multiple distinct storage locations to another storage location.

Claims (75)

1. A system comprising:

a host processor; and

at least one storage device coupled to the host processor;

the host processor being configured to execute instructions of an instruction set, the instruction set comprising a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations, the first move instruction being configured to direct movement of data identified by the at least one operand of the first move instruction into each of the multiple distinct storage locations;

wherein the host processor in executing the first move instruction is configured:

to store the data in a first one of the storage locations identified by one or more additional operands of the first move instruction; and

to store the data in a second one of the storage locations identified based at least in part on the first storage location.

2. The system of claim 1 wherein the host processor comprises a plurality of registers, and wherein the data to be moved by execution of the first move instruction is in a first one of the registers, the first register being identified by at least one operand of the first move instruction.

3. The system of claim 2 wherein the first storage location is identified by an address contained in the one or more additional operands of the first move instruction.

4. The system of claim 3 wherein the second storage location is identified as a function of the address and an offset contained in a second one of the registers.

5. The system of claim 4 wherein the host processor in executing the first move instruction is configured:

to store the data from the first register in the first storage location identified by the address; and

to store the data from the first register in the second storage location identified as a function of the address and the offset.

6. The system of claim 4 wherein the second storage location is identified as a sum of the address and the offset contained in the second register.

7. The system of claim 1 wherein the instruction set further comprises a second move instruction for moving the data from the multiple distinct storage locations to another storage location;

the other storage location being identified by at least one operand of the second move instruction;

wherein the host processor in executing the second move instruction is configured:

to retrieve the data from the first storage location;

to retrieve the data from the second storage location;

to compare the retrieved data from the first storage location with the retrieved data from the second storage location;

responsive to the retrieved data from the first storage location being the same as the retrieved data from the second storage location, to store the data in the other storage location; and

responsive to the retrieved data from the first storage location being different than the retrieved data from the second storage location, to generate a notification indicative of the difference.

8. The system of claim 7 wherein the host processor comprises a plurality of registers, and wherein the other storage location comprises a particular one of the registers identified by at least one operand of the second move instruction.

9. The system of claim 7 wherein retrieving the data from the first and second storage locations comprises:

loading the data from the first storage location into a first hidden register of the host processor; and

loading the data from the second storage location into a second hidden register of the host processor.

10. The system of claim 9 wherein comparing the retrieved data from the first storage location with the retrieved data from the second storage location comprises comparing contents of the first and second hidden registers.

11. The system of claim 7 wherein generating a notification indicative of the difference comprises raising an application level exception.

12. The system of claim 1 wherein the first and second storage locations are in one of:

respective distinct memory blocks of at least one volatile memory of the system; and

respective distinct memory blocks of at least one persistent memory of the system.

13. The system of claim 1 wherein the first and second storage locations are in respective ones of a first memory block in a volatile memory of the system and a second memory block in a persistent memory of the system.

14. The system of claim 1 wherein the first and second storage locations are in respective distinct fault domains of the system.

15. A method comprising:

obtaining in a host processor of a system a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations, the first move instruction being configured to direct movement of data identified by the at least one operand of the first move instruction into each of the multiple distinct storage locations; and

executing the first move instruction in the host processor;

wherein executing the first move instruction comprises:

storing the data in a first one of the storage locations identified by one or more additional operands of the first move instruction; and

storing the data in a second one of the storage locations identified based at least in part on the first storage location.

16. The method of claim 15 wherein:

the host processor comprises a plurality of registers, and the data to be moved by execution of the first move instruction is in a first one of the registers;

the first register being identified by at least one operand of the first move instruction;

the first storage location being identified by an address contained in the one or more additional operands of the first move instruction; and

the second storage location being identified as a function of the address and an offset contained in a second one of the registers.

17. The method of claim 15 further comprising:

obtaining in the host processor a second move instruction for moving the data from the multiple distinct storage locations to another storage location; and

executing the second move instruction in the host processor;

the other storage location being identified by at least one operand of the second move instruction;

wherein executing the second move instruction comprises:

retrieving the data from the first storage location;

retrieving the data from the second storage location;

comparing the retrieved data from the first storage location with the retrieved data from the second storage location;

responsive to the retrieved data from the first storage location being the same as the retrieved data from the second storage location, storing the data in the other storage location; and

responsive to the retrieved data from the first storage location being different than the retrieved data from the second storage location, generating a notification indicative of the difference.

18. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by a system comprising a host processor and at least one storage device coupled to the host processor, causes the system:

to obtain a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations, the first move instruction being configured to direct movement of data identified by the at least one operand of the first move instruction into each of the multiple distinct storage locations; and

to execute the first move instruction in the host processor;

wherein executing the first move instruction comprises:

storing the data in a first one of the storage locations identified by one or more additional operands of the first move instruction; and

storing the data in a second one of the storage locations identified based at least in part on the first storage location.

19. The computer program product of claim 18 wherein:

the host processor comprises a plurality of registers, and the data to be moved by execution of the first move instruction is in a first one of the registers;

the first register being identified by at least one operand of the first move instruction;

the first storage location being identified by an address contained in the one or more additional operands of the first move instruction; and

the second storage location being identified as a function of the address and an offset contained in a second one of the registers.

20. The computer program product of claim 18 wherein the program code when executed by the system further causes the system:

to obtain in the host processor a second move instruction for moving the data from the multiple distinct storage locations to another storage location; and

to execute the second move instruction in the host processor;

the other storage location being identified by at least one operand of the second move instruction;

wherein executing the second move instruction comprises:

retrieving the data from the first storage location;

retrieving the data from the second storage location;

comparing the retrieved data from the first storage location with the retrieved data from the second storage location;

responsive to the retrieved data from the first storage location being the same as the retrieved data from the second storage location, storing the data in the other storage location; and

responsive to the retrieved data from the first storage location being different than the retrieved data from the second storage location, generating a notification indicative of the difference.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (050724/0571) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0088 →
RELEASE OF SECURITY INTEREST AT REEL 050406 FRAME 421 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058213/0825 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 15, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 050724/0571 →
SECURITY AGREEMENT Recorded Sep 17, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 050406/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2019
From: ROBILLARD, MICHAEL; MICHAUD, ADRIAN; SAVIC, DRAGAN
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 049506/0231 →