IP Library Granted Patent US 11,012,041
Granted Patent B2
US 11,012,041 · App. 16/444,610 · Granted May 18, 2021

Differential amplifier circuit

Inventors: Hideyuki Sawai (Chiba, JP); Tsutomu Tomioka (Chiba, JP); Tadakatsu Kuroda (Chiba, JP)
Assignee: ABLIC INC.
H03F3/45183H03F2200/375H03F2203/45042H03F2203/45044H03F2203/45354
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Quick Facts
Patent No.
US 11,012,041
App. No.
16/444,610
Granted
May 18, 2021
Kind
B2
Abstract

A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Claims (20)

1. A differential amplifier circuit comprising:

a first input terminal;

a second input terminal;

a first input transistor containing a gate to receive a first signal supplied from the first input terminal via the gate thereof;

a second input transistor containing a gate to receive a second signal supplied from the second input terminal via the gate thereof; and

an offset voltage adjustment circuit connected to at least one of between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor, the offset voltage adjustment circuit adjusting an offset voltage of the input transistors depending on a generated adjustment voltage,

wherein the offset voltage adjustment circuit includes a first variable resistance circuit containing a plurality of resistances serially connected between the first input terminal and the gate of the first input transistor, and a first current source connected to a connection point between the first variable resistance circuit and the gate of the first input transistor, and

wherein the first current source is configured to supply a current to flow into the first variable resistance circuit and to generate the adjustment voltage.

2. The differential amplifier circuit according to claim 1 , wherein the offset voltage adjustment circuit includes a second variable resistance circuit containing a plurality of resistances serially connected between the second input terminal and the gate of the second input transistor, and a second current source connected to a connection point between the second variable resistance circuit and the gate of the second input transistor, and

wherein the second current source is configured to supply a current to flow into the second variable resistance circuit and to generate the adjustment voltage.

3. A differential amplifier circuit comprising:

a first input terminal;

a second input terminal;

a first input transistor containing a gate to receive a first signal supplied from the first input terminal via the gate thereof;

a second input transistor containing a gate to receive a second signal supplied from the second input terminal via the gate thereof; and

an offset voltage adjustment circuit connected to at least one of between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor, the offset voltage adjustment circuit adjusting an offset voltage of the input transistors depending on a generated adjustment voltage,

wherein the offset voltage adjustment circuit includes a first resistance connected between the first input terminal and the gate of the first input transistor and a first variable current source connected between the first resistance and the gate of the first input transistor, and

wherein the first variable current source is configured to supply a current to flow into the first resistance and to generate the adjustment voltage.

4. The differential amplifier circuit according to claim 3 , wherein the offset voltage adjustment circuit includes a second resistance connected between the second input terminal and the gate of the second input transistor and a second variable current source connected between the second resistance and the gate of the second input transistor, and

wherein the second variable current source is configured to supply a current to flow into the second resistance and to generate the adjustment voltage.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2019
From: SAWAI, HIDEYUKI; TOMIOKA, TSUTOMU; KURODA, TADAKATSU
To: ABLIC INC.
Reel/Frame 049519/0458 →