Adaptive signal synchronization and glitch suppression for encryption engines

1. An artificial reality system comprising:

a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt an encrypted block of data to form a decrypted block of data, wherein at least one of the computational stages included in the pipeline of the decryption data path includes:

multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path; and

a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at the downstream logic element of the at least one computational stage of the decryption data path at substantially a same time;

wherein the first logical path and the second logical path introduce signal traversal asymmetry after an upstream logic element of the at least one computational stage of the decryption data path, and wherein the glitch suppression register is configured to synchronize the first signal and the second signal after the first signal and the second signal traverse the upstream logic element and before the first signal and the second signal arrive at the downstream logic element; and

a head-mounted display (HMD) configured to output artificial reality content including the decrypted block of data.

2. The artificial reality system of claim 1 ,

wherein the glitch suppression register comprises a first bypassable flop included in the first logical path, further comprising a second bypassable flop included in the second logical path, and wherein to synchronize the first signal with respect to the second signal, a control unit is configured to:

enable the first bypassable flop to process the first signal through the bypassable flop; and

disable the second bypassable flop such that the second signal bypasses the bypassable flop.

3. The artificial reality system of claim 2 , further comprising a decryption engine that includes the decryption datapath, wherein the bypassable flop includes a primary latch, a secondary latch, and a multiplexer (MUX), and wherein to pass the first signal through the bypassable flop, the control unit is configured to:

based on a determination that the decryption engine is presently operating at a full frequency:

enable both of the primary latch and the secondary latch to process the first signal; and

multiplex respective outputs of the primary latch and the secondary latch.

4. The artificial reality system of claim 2 , further comprising a decryption engine that includes the decryption datapath, wherein the bypassable flop includes a primary latch, a secondary latch, and a multiplexer (MUX), and wherein to pass the first signal through the bypassable flop, the control unit is configured to:

based on a determination that the decryption engine is presently operating at a reduced frequency:

enable the primary latch to process the first signal; and

disable the secondary latch from processing the first signal.

5. The artificial reality system of claim 1 , wherein the upstream logic element comprises an inversion unit and the downstream logic element comprises a multiplication unit, wherein the first signal provides a first operand to the multiplication unit, and wherein the second signal provides a second operand to the multiplication unit.

6. The artificial reality system of claim 1 , wherein the at least one computational stage of the decryption data path comprises a substitute byte (Sbox) unit of the decryption data path.

7. The artificial reality system of claim 1 , further comprising a decryption engine that includes the decryption datapath, wherein the decryption engine is integrated into the HMD.

8. A decryption integrated circuit (IC) comprising:

an interface configured to receive an encrypted block of data; and

a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt the encrypted block of data to form a decrypted block of data wherein at least one computational stage included in the pipeline of the decryption data path includes:

multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path; and

a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at a downstream logic element of the at least one computational stage of the decryption data path at substantially a same time;

wherein the first logical path and the second logical path introduce signal traversal asymmetry after an upstream logic element of the at least one computational stage of the decryption data path, and wherein the glitch suppression register is configured to synchronize the first signal and the second signal after the first signal and the second signal traverse the upstream logic element and before the first signal and the second signal arrive at the downstream logic element.

9. The decryption IC of claim 8 , wherein the glitch suppression register comprises a first bypassable flop included in the first logical path, further comprising a second bypassable flop included in the second logical path, and wherein to synchronize the first signal with respect to the second signal, a control unit is configured to:

enable the first bypassable flop to process the first signal through the bypassable flop; and

disable the second bypassable flop such that the second signal bypasses the bypassable flop.

10. The decryption IC of claim 9 , wherein the bypassable flop includes a primary latch, a secondary latch, and a multiplexer (MUX), and wherein to pass the first signal through the bypassable flop, the control unit is configured to:

based on a determination that the decryption engine is presently operating at a full frequency:

enable both of the primary latch and the secondary latch to process the first signal; and

multiplex respective outputs of the primary latch and the secondary latch.

11. The decryption IC of claim 9 , wherein the bypassable flop includes a primary latch, a secondary latch, and a multiplexer (MUX), and wherein to pass the first signal through the bypassable flop, the control unit is configured to:

based on a determination that the decryption engine is presently operating at a reduced frequency:

enable the primary latch to process the first signal; and

disable the secondary latch from processing the first signal.

12. The decryption IC of claim 8 , wherein the upstream logic element comprises an inversion unit and the downstream logic element comprises a multiplication unit, wherein the first signal provides a first operand to the multiplication unit, and wherein the second signal provides a second operand to the multiplication unit.

13. The decryption IC of claim 8 , wherein the at least one computational stage of the decryption data path comprises a substitute byte (Sbox) unit of the decryption data path of the decryption engine.

14. An apparatus for data decryption, the apparatus comprising:

an interface configured to receive an encrypted block of data; and

a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt the encrypted block of data to form a decrypted block of data, wherein at least one of the computational stages included in the pipeline of the decryption data path includes:

multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path; and

a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at a downstream logic element of the at least one computational stage of the decryption data path at substantially a same time;

wherein the first logical path and the second logical path introduce signal traversal asymmetry after an upstream logic element of the at least one computational stage of the decryption data path, and wherein the glitch suppression register is configured to synchronize the first signal and the second signal after the first signal and the second signal traverse the upstream logic element and before the first signal and the second signal arrive at the downstream logic element.

15. The apparatus of claim 14 , wherein the glitch suppression register comprises a first bypassable flop included in the first logical path, further comprising a second bypassable flop included in the second logical path, and wherein to synchronize the first signal with respect to the second signal, a control unit is configured to:

enable the first bypassable flop to process the first signal through the bypassable flop; and

disable the second bypassable flop such that the second signal bypasses the bypassable flop.

16. The apparatus of claim 14 , wherein the apparatus is a system on a chip (SoC).

17. The apparatus of claim 16 , wherein the SoC is configured to support an artificial reality application.

18. An artificial reality system comprising:

a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt an encrypted block of data to form a decrypted block of data, wherein at least one of the computational stages included in the pipeline of the decryption data path includes:

multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path; and

a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at the downstream logic element of the at least one computational stage of the decryption data path at substantially a same time;

wherein the glitch suppression register comprises a first bypassable flop included in the first logical path, further comprising a second bypassable flop included in the second logical path, and wherein to synchronize the first signal with respect to the second signal, a control unit is configured to:

enable the first bypassable flop to process the first signal through the bypassable flop; and

disable the second bypassable flop such that the second signal bypasses the bypassable flop; and

a head-mounted display (HMD) configured to output artificial reality content including the decrypted block of data.