Methods and system for an integrated circuit

1. An integrated circuit, comprising:

a first input terminal adapted to receive a data signal;

a second input terminal adapted to receive a clock signal;

a counter circuit adapted to generate a count value according to an oscillator;

an interface circuit connected to the first and second input terminals, and comprising:

a compare circuit; and

a plurality of flip-flop circuits;

wherein the compare circuit and the flip-flop circuits are adapted to operate together to generate a write protect signal;

a register in communication with the interface circuit and adapted to:

store an address; and

receive the write protect signal from the interface circuit;

wherein the write protect signal prevents changes to the address.

2. The integrated circuit according to claim 1 , wherein the interface circuit comprises:

a first flip-flop circuit, from the plurality of flip-flop circuits, connected to the first input terminal and adapted to receive the data signal; and

a second flip-flop circuit, from the plurality of flip-flop circuits, connected to the second input terminal and adapted to generate an output signal.

3. The integrated circuit according to claim 2 , wherein the compare circuit is adapted to generate the write protect signal according to the input signal and the output signal.

4. The integrated circuit according to claim 1 , wherein the write protect signal comprises a high value and a low value.

5. The integrated circuit according to claim 4 , wherein the write protect signal prevents changes to the address when:

the output signal is a high value;

the input signal is a low value; and

the write protect signal is the high value.

6. The integrated circuit according to claim 1 , further comprising a non-volatile memory in communication with the register.

7. The integrated circuit according to claim 1 , wherein the address of the register comprises one of: a default address and a new address.

8. The integrated circuit according to claim 7 , wherein the interface is adapted to change the address of the register from the default address to the new address.

9. A method for assigning addresses to plurality of slave devices, comprising:

generating, with a host device, a first communication signal using a default address;

transmitting the first communication signal to each slave device from the plurality of slave devices;

generating, with the plurality of slave devices, a plurality of first acknowledgment signals;

transmitting the plurality of first acknowledgment signals to the host device;

generating, with the plurality of slave devices, a plurality of first counter values, wherein each first counter value is generated according to a counter circuit;

transmitting the plurality of first counter values to the host device;

identifying a counter value, from the plurality of first counter values, as a lowest-magnitude counter value; and

writing a first new address to the slave device associated with the lowest-magnitude counter value from the plurality of first counter values.

10. The method according to claim 9 , further comprising:

generating, with the host device, a second communication signal using the default address;

transmitting the second communication signal to each slave device from the plurality of slave devices;

generating, with a portion of the plurality of slave devices, a plurality of second acknowledgment signals;

transmitting the plurality of second acknowledgment signals to the host device;

generating, with the portion of the plurality of slave devices, a plurality of second counter values, wherein each second counter value is generated according to the counter circuit;

transmitting the plurality of second counter values to the host device;

identifying a counter value, from the plurality of second counter value, as a lowest-magnitude counter value; and

writing a second new address to the slave device associated with the lowest-magnitude counter value from the plurality of second counter value.

11. The method according to claim 9 , further comprising generating a non-acknowledgment signal and transmitting the non-acknowledgement signal to the host device.

12. The method according to claim 9 , wherein the plurality of slave devices are connected to the host device via a common bus.

13. The method according to claim 9 , further comprising preventing address changes to the slave devices associated with counter values other than the lowest-magnitude counter value.

14. A system, comprising:

a host device; and

a plurality of integrated circuits connected to the host device via a common bus, wherein:

each integrated circuit comprises:

a first input terminal adapted to receive a data signal;

a second input terminal adapted to receive a clock signal; and

a counter circuit adapted to generate a count value according to an oscillator;

an interface circuit connected to the first and second input terminals and adapted to generate a write protect signal;

a register in communication with the interface circuit and adapted to:

store an address, wherein the address is one of a default address and a new address; and

receive the write protect signal from the interface circuit, wherein the write protect signal prevents changes to one of the default address and the new address;

each drive integrated circuit is connected to the host device via:

the first input terminal in conjunction with a first line; and

the second input terminal in conjunction with a second line;

wherein the host device is adapted to communicate with each integrated circuit according to the default address and replace the default address with a new address.

15. The system according to claim 14 , wherein the interface circuit comprises:

a first flip-flop circuit connected to the first input terminal and adapted to receive the data signal; and

a second flip-flop circuit connected to the second input terminal and adapted to generate an output signal.

16. The system according to claim 15 , wherein the compare circuit is adapted to generate the write protect signal according to the input signal and the output signal.

17. The system according to claim 14 , further comprising a non-volatile memory in communication with the register.

18. The system according to claim 14 , wherein the host device is adapted to:

generate a communication signal using the default address; and

transmit the communication signal to each integrated circuit from the plurality of integrated circuits.

19. The system according to claim 14 , wherein each integrated circuit is adapted to:

generate an acknowledgment signal;

transmit the acknowledgment signal to the host device;

generate a counter value according to the counter circuit; and

transmit the counter value to the host device.

20. The system according to claim 14 , wherein the host device is further adapted to:

identify a single counter value, from a plurality of counter values, as a lowest-magnitude counter value; and

assign a new address to the integrated circuit associated with the lowest-magnitude counter value from the plurality of counter values.