Methods and apparatus for an amplifier integrated circuit

1. An amplifier integrated circuit (IC), comprising:

a first set of series-connected transistors connected to:

a first node having a supply voltage potential;

a second node having a first bias potential;

a third node having a second bias potential; and

a fourth node having a third bias potential;

wherein the first, second, and third bias potentials have values that are different from each other;

a second set of series-connected transistors connected:

in parallel with the first set of transistors; and

to the first node;

a third set of series-connected transistors connected to the first node;

a fourth set of series-connected transistors connected:

in parallel with the third set of transistors; and

to the first node;

a first switching circuit connecting the first set of transistors to the second set of transistors; and

a second switching circuit connecting the third set of transistors to the fourth set of transistors.

2. The amplifier integrated circuit according to claim 1 , wherein:

the second set of transistors is connected to each of the second, third, and fourth nodes;

the third set of transistors is connected to each of the second, third, and fourth nodes; and

the fourth set of transistors is connected to each of the second, third, and fourth nodes.

3. The amplifier integrated circuit according to claim 1 , wherein:

a first transistor, from the first set of transistors, comprises a first gate terminal that is connected to the second node;

a second transistor, from the first set of transistors, comprises a second gate terminal that is connected to the third node; and

a third transistor, from the first set of transistors, comprises a third gate terminal that is connected to the fourth node.

4. The amplifier integrated circuit according to claim 1 , wherein:

a first transistor, from the second set of transistors, comprises a first gate terminal that is connected to the second node;

a second transistor, from the second set of transistors, comprises a second gate terminal that is connected to the third node; and

a third transistor, from the second set of transistors, comprises a third gate terminal that is connected to the fourth node.

5. The amplifier integrated circuit according to claim 1 , wherein:

a first transistor, from the third set of transistors, comprises a first gate terminal that is connected to the second node;

a second transistor, from the third set of transistors, comprises a second gate terminal that is connected to the third node; and

a third transistor, from the third set of transistors, comprises a third gate terminal that is connected to the fourth node.

6. The amplifier integrated circuit according to claim 1 , wherein:

a first transistor, from the fourth set of transistors, comprises a first gate terminal that is connected to the second node;

a second transistor, from the fourth set of transistors, comprises a second gate terminal that is connected to the third node; and

a third transistor, from the fourth set of transistors, comprises a third gate terminal that is connected to the fourth node.

7. The amplifier integrated circuit according to claim 1 , wherein the first switching circuit comprises:

a first switch connected between a first transistor from the first set of transistors and a first transistor from the second set of transistors;

a second switch connected between a second transistor from the first set of transistors and a second transistor from the second set of transistors;

a third switch connected between a third transistor from the first set of transistors and a third transistor from the second set of transistors; and

a fourth switch connected between a fourth transistor from the first set of transistors and a fourth transistor from the second set of transistors.

8. The amplifier integrated circuit according to claim 1 , wherein the second switching circuit comprises:

a first switch connected between a first transistor from the third set of transistors and a first transistor from the fourth set of transistors;

a second switch connected between a second transistor from the third set of transistors and a second transistor from the fourth set of transistors;

a third switch connected between a third transistor from the third set of transistors and a third transistor from the fourth set of transistors; and

a fourth switch connected between a fourth transistor from the third set of transistors and a fourth transistor from the fourth set of transistors.

9. A method for providing an amplifier integrated circuit with variable gain bandwidth product, comprising:

generating a first output with the amplifier integrated circuit according to a first gain bandwidth product, comprising:

generating a first current through a first set of series-connected transistors and a fourth set of series-connected transistors, comprising:

applying a plurality of bias potentials to the first and fourth sets of series-connected transistors, wherein bias potentials have different values from each other; and

applying a supply voltage potential to the first and fourth sets of series-connected transistors; and

generating a second output with the amplifier integrated circuit according to a second gain bandwidth product, comprising:

generating the first current through the first set of series-connected transistors by applying the plurality of bias potentials and the supply voltage potential to the first set of series-connected transistors; and

generating a second current through a second set of series-connected transistors and a third set of series-connected transistors, comprising:

applying the supply voltage potential to the second and third sets of series-connected transistors;

connecting the first set of transistors to the second set of transistors; and

connecting the third set of transistors to the fourth set of transistors.

10. The method according to claim 9 , wherein:

the plurality of bias potentials comprises:

a first bias potential;

a second bias potential; and

a third bias potential.

11. The method according to claim 10 , wherein the values of the plurality of bias potentials remain constant when the amplifier integrated circuit generates the first and second outputs.

12. The method according to claim 11 , wherein the amplifier integrated circuit generates the first and second outputs in sequence while the amplifier integrated circuit is ON.

13. A system, comprising:

a sensor configured to generate sensor data;

an amplifier integrated circuit (IC) comprising:

a main input terminal configured to receive the sensor data; and

a main output terminal;

wherein the amplifier IC is configured to:

generate a first output signal according to a first gain bandwidth product; and

generate a second output signal according to a second gain bandwidth product and in sequence with the first output signal while the amplifier IC is ON, wherein the second gain bandwidth is less than the first gain bandwidth product; and

a switched capacitor circuit connected to the main output terminal and configured to charge according to the first and second output signals.

14. The system according to claim 13 , wherein the amplifier IC comprises:

a first set of series-connected transistors connected to a first node having a supply voltage potential;

a second set of series-connected transistors connected:

in parallel with the first set of transistors; and

to the first node;

a third set of series-connected transistors connected to the first node;

a fourth set of series-connected transistors connected:

in parallel with the third set of transistors; and

to the first node;

a first switching circuit connecting the first set of transistors to the second set of transistors; and

a second switching circuit connecting the third set of transistors to the fourth set of transistors.

15. The system according to claim 14 , wherein:

the first switching circuit comprises:

a first switch connected between a first transistor from the first set of transistors and a first transistor from the second set of transistors;

a second switch connected between a second transistor from the first set of transistors and a second transistor from the second set of transistors;

a third switch connected between a third transistor from the first set of transistors and a third transistor from the second set of transistors; and

a fourth switch connected between a fourth transistor from the first set of transistors and a fourth transistor from the second set of transistors; and

the second switching circuit comprises:

a first switch connected between a first transistor from the third set of transistors and a first transistor from the fourth set of transistors;

a second switch connected between a second transistor from the third set of transistors and a second transistor from the fourth set of transistors;

a third switch connected between a third transistor from the third set of transistors and a third transistor from the fourth set of transistors; and

a fourth switch connected between a fourth transistor from the third set of transistors and a fourth transistor from the fourth set of transistors.

16. The system according to claim 14 , wherein the amplifier IC further comprises:

a second node having a first bias potential;

a third node having a second bias potential; and

a fourth node having a third bias potential;

wherein the first, second, and third bias potentials have values that are different from each other.

17. The system according to claim 16 , wherein the values of the first, second, and third bias potentials remain constant when the amplifier IC generates the first and second outputs.

18. The system according to claim 16 , wherein:

the first set of transistors is connected to each of the second, third, and fourth nodes;

the second set of transistors is connected to each of the second, third, and fourth nodes;

the third set of transistors is connected to each of the second, third, and fourth nodes; and

the fourth set of transistors is connected to each of the second, third, and fourth nodes.

19. The system according to claim 13 , wherein the amplifier IC is further configured to charge the switched capacitor for a first period according to the first output signal and charge the switched capacitor for a second period according to the second output signal.