Current-mode logic latches for a PVT-robust mod 3 frequency divider
View Patent ↗An illustrative digital latch includes: a differential transistor pair (“track pair”) capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted; a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted; a differential transistor pair (“clock pair”) that steers a bias current between the track pair and the latch pair; and a matched set of bias transistors that determines the bias current for the clock pair and a reference voltage on a reference voltage node, the reference voltage node being coupled to a base of each transistor in the track pair by equal bias resistances.
1. An integrated circuit on a semiconductor substrate, the integrated circuit including a digital latch that comprises:
a differential transistor pair (“track pair”) capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted;
a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted;
a differential transistor pair (“clock pair”) that, responsive to the clock signal, steers a bias current between a shared emitter node of the track pair and a shared emitter node of the latch pair; and
a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set including:
a first bias transistor that determines the bias current for the clock pair; and
a second bias transistor that sources or sinks an equal bias current through a load resistance to determine a reference voltage on a reference voltage node,
the reference voltage node being coupled to a base of each transistor in the track pair by a bias resistance proportional to each of said base resistances to provide a bias voltage.
2. The integrated circuit of claim 1 , wherein a voltage on the shared bias voltage node is determined by a bandgap voltage reference.
3. The integrated circuit of claim 1 , wherein each of the output nodes is coupled to a supply voltage by a pull-up resistance equal to the load resistance.
4. The integrated circuit of claim 1 , further comprising a first pair of emitter-follower-configured transistors that amplify the clock signal to drive gates of the transistors in the clock pair, the emitter-follower-configured transistors being biased by respective bias transistors in the matched set.
5. The integrated circuit of claim 4 , further comprising a second pair of emitter-follower-configured transistors that buffer the differential output voltage for output, the emitter-follower-configured transistors in the second pair each being biased by respective bias transistors in the matched set.
6. The integrated circuit of claim 1 , wherein at least one of the transistors in the clock pair is implemented with a triple-well architecture, and wherein the integrated circuit further comprises a choke resistor that reverse-biases an isolation well in the triple-well architecture.
7. The integrated circuit of claim 1 , further comprising:
a first master latch coupled to provide said differential input signal to said digital latch to implement a first flip flop; and
a second flip flop including:
a second master latch; and
a slave latch capacitively coupled to receive output from the second master latch and coupled to provide a capacitively coupled differential input signal to the first master latch.
8. The integrated circuit of claim 7 , wherein the second master latch is capacitively coupled to receive a first output signal from the digital latch and capacitively coupled to receive a second output signal from the slave latch, and wherein the second master latch produces a third output signal that is a logical NOR of the first output signal and the second output signal.
9. An integrated circuit on a semiconductor substrate, the integrated circuit including a modified digital latch that comprises:
an input transistor arrangement that includes:
a first input transistor having a base capacitively coupled to receive a first input signal;
a second input transistor having a base capacitively coupled to receive a second input signal; and
a complementary transistor having a base capacitively coupled to a fixed voltage node, the input transistor arrangement producing a differential output voltage between output nodes when a clock signal is asserted, the differential output voltage representing a logical NOR of the first and second input signals;
a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted;
a differential transistor pair (“clock pair”) that, responsive to the clock signal, steers a bias current between a shared emitter node of the track pair and a shared emitter node of the latch pair; and
a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set including:
a first bias transistor that determines the bias current for the clock pair; and
a second bias transistor that sources or sinks an equal bias current through a load resistance to determine a reference voltage on a reference voltage node,
the reference voltage node being coupled to a base of each transistor in the input transistor arrangement by a bias resistance proportional to each of said base resistances to provide a bias voltage.
10. The integrated circuit of claim 9 , wherein a voltage on the shared bias voltage node is determined by a bandgap voltage reference.
11. The integrated circuit of claim 9 , wherein each of the output nodes is coupled to a supply voltage by a pull-up resistance equal to the load resistance.
12. The integrated circuit of claim 9 , further comprising a first pair of emitter-follower-configured transistors that amplify the clock signal to drive gates of the transistors in the clock pair, the emitter-follower-configured transistors being biased by respective bias transistors in the matched set.
13. The integrated circuit of claim 12 , further comprising a second pair of emitter-follower-configured transistors that buffer the differential output voltage for output, the emitter-follower-configured transistors in the second pair each being biased by respective bias transistors in the matched set.
14. The integrated circuit of claim 9 , wherein at least one of the transistors in the clock pair is implemented with a triple-well architecture, and wherein the integrated circuit further comprises a choke resistor that reverse-biases an isolation well in the triple-well architecture.
15. The integrated circuit of claim 9 , further comprising:
a slave latch coupled to the modified digital latch to implement a flip flop, the flip flop providing a differential output between a positive output node and a negative output node.
16. The integrated circuit of claim 15 , wherein the positive output node is coupled to the first input transistor as the first input signal, and wherein the modified digital latch further comprises a third input transistor having a base capacitively coupled to the negative output node to match loading of the positive output node.
17. A method of manufacturing a digital latch, the method comprising:
capacitively coupling bases of a differential transistor pair (“track pair”) to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted;
connecting a cross-coupled transistor pair (“latch pair”) to the output nodes to latch the differential output voltage when the clock signal is de-asserted;
providing a differential transistor pair (“clock pair”) that, responsive to the clock signal, steers a bias current between a shared emitter node of the track pair and a shared emitter node of the latch pair; and
biasing with a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set including:
a first bias transistor that determines the bias current for the clock pair; and
a second bias transistor that sources or sinks an equal bias current through a load resistance to determine a reference voltage on a reference voltage node,
the reference voltage node being coupled to a base of each transistor in the track pair by a bias resistance proportional to each of said base resistances to provide a bias voltage.
18. The method of claim 17 , further comprising: coupling each of the output nodes to a supply voltage by a pull-up resistance equal to the load resistance.
19. The method of claim 17 , further comprising: implementing the clock pair using a triple-well architecture; and reverse-biasing an isolation well in the triple-well architecture via a choke resistor.
20. The method of claim 17 , further comprising: using bias transistors from the matched set to bias a first pair of emitter-follower-configured transistors that amplify the clock signal to drive gates of the transistors in the clock pair, and to bias a second pair of emitter-follower-configured transistors that buffer the differential output voltage for output.