Self-aligned trench MOSFET contacts having widths less than minimum lithography limits
Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
1. A semiconductor device, comprising:
a silicon substrate comprising a surface;
a gate electrode formed in a gate trench extending into the substrate from the surface;
a channel region adjacent to the gate electrode comprising a non-uniform channel dopant profile;
a source region adjacent to the gate electrode between the surface and the channel region, comprising a non-uniform source dopant profile;
an insulator layer formed above the substrate; and
a source contact extending through the insulator layer, wherein the source contact comprises a width that is less than a minimum lithography limit for a processing capability.
2. The semiconductor device of claim 1 , wherein the channel dopant profile comprises a curved profile, wherein a dopant concentration directly below the source contact is lower than a dopant concentration further from the source contact.
3. The semiconductor device of claim 1 , wherein the source dopant profile comprises a curved profile, wherein a dopant concentration directly below the source contact is lower than a dopant concentration further from the source contact.
4. The semiconductor device of claim 1 , wherein the source contact is self-aligned with the gate electrode.
5. The semiconductor device of claim 1 , comprising a Si mesa width less than 200 nm.
6. The semiconductor device of claim 1 , comprising a gate trench width of less than 100 nm.
7. The semiconductor device of claim 1 , wherein the source contact extends through the source region and contacts the channel region.
8. The semiconductor device of claim 1 , comprising a ratio of the width of the body region to a width of the source region that is greater than two.
9. The semiconductor device of claim 1 , comprising an additional gate electrode formed in an additional gate trench located opposite the channel from the gate trench.