Electrical interconnection of image sensor package
Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.
1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
an active area comprised on the second side of the die;
two or more interconnect bumps coupled to two or more die pads on the second side of the die;
an optically transmissive lid coupled to the semiconductor die through an adhesive, the two or more interconnect bumps, and a first redistribution layer (RDL); and
a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die and extending to the first side of the semiconductor die;
wherein the first RDL extends to an edge of the semiconductor die; and
wherein the two or more interconnect bumps are copper pillars comprising solder tips.
2. The semiconductor package of claim 1 , wherein a pad pitch of the two or more interconnect bumps is substantially 60 microns.
3. The semiconductor package of claim 1 wherein a pad pitch of the two or more interconnect bumps is substantially 70 microns.
4. The semiconductor package of claim 1 , wherein one or more side walls of the semiconductor die are angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die.
5. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
an active area comprised on the second side of the die;
two or more copper pillars coupled to the second side of the die on either side of the active area;
a first redistribution layer (RDL) coupled to each of the two or more copper pillars and extending to an edge of the semiconductor die;
an optically transmissive lid coupled to the semiconductor die through the two or more copper pillars and the first RDL; and
a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die, the second RDL extending to the first side of the semiconductor die; and
wherein the two or more copper pillars comprise solder tips.
6. The semiconductor package of claim 5 , wherein the two or more copper pillars are coupled to two or more die pads.
7. The semiconductor package of claim 5 , wherein a pad pitch of the two or more copper pillars is substantially 60 microns.
8. The semiconductor package of claim 5 , wherein a pad pitch of the two or more copper pillars is substantially 70 microns.
9. The semiconductor package of claim 5 , wherein one or more sidewalls of the semiconductor die are angled between 85 degrees and 60 degrees from a plane formed by the first side of the semiconductor die.