Low latency post-quantum signature verification for fast secure-boot
In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
1. An apparatus, comprising:
a computer readable memory;
an XMSS verification manager logic to manage XMSS verification functions;
a one-time signature and public key generator logic;
a chain function logic to implement chain function algorithms;
a low latency SHA3 hardware engine capable to perform a SHAKE-128 function or to perform a SHAKE-256 operation, the SHA3 hardware engine comprising a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a 256 bit message input; and
a register bank communicatively coupled to the XMSS verification manager logic.
2. The apparatus of claim 1 , further comprising logic to:
receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and
apply the set of XMSS inputs to an XMSS verification manager logic.
3. The apparatus of claim 2 , further comprising logic to:
assert a busy signal on a communication bus; and
switch to a protected mode in which external read/write operations are disregarded.
4. The apparatus of claim 3 , further comprising logic to:
apply a one-time signature function process to the set of XMSS inputs; and
invoke the chain function logic to apply a chain function to facilitate the one-time signature function.
5. The apparatus of claim 1 , wherein the SHA3 hardware engine comprises logic to:
perform a first set of 24 SHA3 rounds using the first set of inputs; and
generate a first 128 bit output.
6. The apparatus of claim 5 , wherein the SHA3 hardware engine comprises logic to:
perform a second set of 24 SHA3 rounds using no inputs; and
generate a second 128 bit output.
7. The apparatus of claim 1 , wherein the SHA3 hardware engine comprises logic to:
perform a first set of 24 SHA3 rounds using the first set of inputs; and
generate a first 256 bit output.
8. The apparatus of claim 7 , wherein the SHA3 hardware engine comprises logic to:
perform a second set of 24 SHA3 rounds using no inputs; and
generate a second 256 bit output.
9. An electronic device, comprising:
a processor; and
a hardware accelerator for an authentication logic, the hardware accelerator comprising:
a computer readable memory;
an XMSS verification manager logic to manage XMSS verification functions;
a one-time signature and public key generator logic;
a chain function logic to implement chain function algorithms;
a low latency SHA3 hardware engine capable to perform a SHAKE-128 function or to perform a SHAKE-256 operation, the SHA3 hardware engine comprising a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a 256 bit message input; and
a register bank communicatively coupled to the XMSS verification manager logic.
10. The electronic device of claim 9 , the hardware accelerator further comprising logic to:
receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and
apply the set of XMSS inputs to an XMSS verification manager logic.
11. The electronic device of claim 10 , the hardware accelerator further comprising logic to:
assert a busy signal on a communication bus; and
switch to a protected mode in which external read/write operations are disregarded.
12. The electronic device of claim 11 , the hardware accelerator further comprising logic to:
apply a one-time signature function process to the set of XMSS inputs; and
invoke the chain function logic to apply a chain function to facilitate the one-time signature function.
13. The electronic device of claim 9 , wherein the SHA3 hardware engine comprises logic to:
perform a first set of 24 SHA3 rounds using the first set of inputs; and
generate a first 128 bit output.
14. The electronic device of claim 13 , wherein the SHA3 hardware engine comprises logic to:
perform a second set of 24 SHA3 rounds using no inputs; and
generate a second 128 bit output.
15. The electronic device of claim 9 , wherein the SHA3 hardware engine comprises logic to:
perform a first set of 24 SHA3 rounds using the first set of inputs; and
generate a first 256 bit output.
16. The electronic device of claim 15 , wherein the SHA3 hardware engine comprises logic to:
perform a second set of 24 SHA3 rounds using no inputs; and
generate a second 256 bit output.