Power factor correction at switched mode power supply
Embodiments of a method and a device are disclosed. In an embodiment, a method for power factor correction (PFC) at a switched mode power supply (SMPS) is disclosed. The method involves receiving an input voltage, generating a reference waveform that is in phase with the input voltage, determining a time value for phase-shifting a PFC current signal, scaling the time value with a phase factor to generate a scaled time value, phase-shifting the reference waveform according to the scaled time value to generate a phase-shifted reference waveform, and generating the PFC current signal based on the phase-shifted reference waveform.
1. A method for power factor correction (PFC) at a switched mode power supply (SMPS), the method comprising:
receiving an input voltage;
generating a reference waveform that is in phase with the input voltage;
determining a time value for phase-shifting a PFC current signal;
scaling the time value with a phase factor to generate a scaled time value;
phase-shifting the reference waveform according to the scaled time value to generate a phase-shifted reference waveform; and
generating the PFC current signal based on the phase-shifted reference waveform.
2. The method of claim 1 , wherein the time value is determined according to an equation:
time value=arctan( C*ω*Vac/Iac )/ω,
where C is a total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS, ω is a frequency of the input voltage, Vac is the input voltage, and Iac is a regulating current signal.
3. The method of claim 2 , wherein the regulating current signal regulates an output voltage of the SMPS to a target reference voltage.
4. The method of claim 1 , wherein the phase factor is a value greater than 0 and less than 1.
5. The method of claim 1 , wherein generating the PFC current signal based on the phase-shifted reference waveform comprises:
multiplying the phase-shifted reference waveform with a regulating current signal to generate a phase-shifted current signal; and
rectifying the phase-shifted current signal to generate the PFC current signal.
6. The method of claim 5 , further comprising outputting the PFC current signal when:
both the input voltage and a voltage of the phase-shifted reference waveform have a value greater than zero; or
both the input voltage and the voltage of the phase-shifted reference waveform have a value less than zero.
7. The method of claim 1 , wherein the SMPS includes a power stage, the method further comprising:
receiving the PFC current signal at a pulse width modulator (PWM) in the power stage; and
outputting a PWM signal from the PWM to a switch such that an average current in an inductor in the power stage is equal to the PFC current signal.
8. The method of claim 1 , wherein determining the time value for phase-shifting the PFC current signal comprises:
generating an input current waveform based on a frequency of the input voltage and a regulating current signal;
generating a capacitor current waveform based on the input voltage, the frequency of the input voltage, and a total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS;
comparing the capacitor current waveform to the input current waveform; and
determining the time value based on a time when the input current waveform is equal to the capacitor current waveform.
9. The method of claim 8 , wherein the input current waveform is generated according to an equation:
input current waveform= Iac *sin(ω t ),
where Iac is the regulating current signal, ω is the frequency of the input voltage, and t is a value greater than 0.
10. The method of claim 8 , wherein the capacitor current waveform is generated according to an equation:
capacitor current waveform= C*ω*Vac *cos(ω t ),
where C is the total capacitance of the one or more EMI filter capacitors, ω is the frequency of the input voltage, Vac is the input voltage, and t is a value greater than 0.
11. A switched mode power supply (SMPS) configured for power factor correction (PFC), comprising:
a reference signal generating circuit configured to receive an input voltage and generate a reference waveform that is in phase with the input voltage;
a processing circuit configured to determine a time value for phase-shifting a PFC current signal;
a scaling circuit configured to scale the time value with a phase factor to generate a scaled time value;
a phase-shifted signal generating circuit configured to phase-shift the reference waveform according to the scaled time value to generate a phase-shifted reference waveform; and
a PFC signal generating circuit configured to generate the PFC current signal based on the phase-shifted reference waveform.
12. The SMPS of claim 11 , wherein the processing circuit is configured to determine the time value according to an equation:
time value=arctan( C*ω*Vac/Iac )/ω,
where C is a total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS, ω is a frequency of the input voltage, Vac is the input voltage, and Iac is a regulating current signal.
13. The SMPS of claim 12 , wherein the regulating current signal regulates an output voltage of the SMPS to a target reference voltage.
14. The SMPS of claim 11 , wherein the phase factor is a value greater than 0 and less than 1.
15. The SMPS of claim 11 , wherein the PFC signal generating circuit configured to generate the PFC current signal is further configured to:
multiply the phase-shifted reference waveform with the regulating current signal to generate a phase-shifted current signal; and
rectify the phase-shifted current signal to generate the PFC current signal.
16. The SMPS of claim 15 , further comprising a switching circuit configured to output the PFC current signal when:
both the input voltage and a voltage of the phase-shifted reference waveform have a value greater than zero; or
both the input voltage and the voltage of the phase-shifted reference waveform have a value less than zero.
17. The SMPS of claim 11 , further comprising:
a power stage comprising a pulse width modulator (PWM), a switch coupled to the PWM, and an inductor coupled to the switch,
wherein the PWM is configured to:
receive the PFC current signal, and
output a PWM signal to the switch such that an average current in the inductor is equal to the PFC current signal.
18. The SMPS of claim 11 , wherein the processing circuit configured to determine the time value is further configured to:
generate an input current waveform based on a frequency of the input voltage and a regulating current signal;
generate a capacitor current waveform based on the input voltage, the frequency of the input voltage, and a total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS;
compare the capacitor current waveform to the input current waveform; and
determine the time value based on a time when the input current waveform is equal to the capacitor current waveform.
19. The SMPS of claim 18 , wherein the processing circuit is configured to generate the input current according to an equation:
input current waveform= Iac *sin(ω t ),
where Iac is the regulating current signal, ω is the frequency of the input voltage, and t is a value greater than 0.
20. The SMPS of claim 18 , wherein the processing circuit is configured to generate the capacitor current waveform according to an equation:
capacitor current waveform= C*ω*Vac *cos(ω t ),
where C is the total capacitance of the one or more EMI filter capacitors, ω is the frequency of the input voltage, Vac is the input voltage, and t is a value greater than 0.