DPLL with adjustable delay in integer operation mode
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
1. An apparatus of a wireless device, the apparatus comprising:
one or more processors, configured to:
in a first mode:
measure a respective delay value for a plurality of delay elements of a digital phase-locked loop (DPLL);
select a delay element of the plurality of delay elements based on a collective delay value between adjacent delay elements of the plurality of delay elements; and
set an initial phase difference value to a phase difference value associated with the selected delay element; and
in a second mode:
initialize the DPLL using the initial phase difference value; and
determine a phase error between a reference clock and a feedback clock based on the initial phase difference value; and
adjust an output clock signal based on the phase error.
2. The apparatus according to claim 1 , wherein the plurality of delay elements are serially-coupled delay elements.
3. The apparatus according to claim 2 , wherein the plurality of delay elements includes serially-coupled inverter circuits.
4. The apparatus according to claim 1 , wherein the DPLL includes:
a time-to-digital converter (TDC) to compare a phase of the reference clock to a phase of the feedback clock to provide a delay value using the plurality of delay elements; and
a lookup table to determine a phase estimation value based on the delay value.
5. The apparatus according to claim 4 , wherein the DPLL further includes a digital phase detector (DPD) to determine a phase error based on a change in the phase estimation value.
6. The apparatus according to claim 5 , wherein the one or more processors are configured to cause the DPD to:
calculate an instantaneous frequency based on the change in the estimated phase difference value;
compare the instantaneous frequency to a desired frequency to determine a frequency error; and
integrate the frequency error to determine the phase error.
7. The apparatus according to claim 5 , wherein the DPLL further includes:
a loop filter to provide a frequency correction command based on the phase error; and
a controlled oscillator to provide the output clock signal based on the frequency correction command.
8. The apparatus according to claim 7 , wherein the controlled oscillator includes one of a voltage-controlled oscillator or a digital-controlled oscillator.
9. The apparatus according to claim 1 , further comprising transceiver circuitry to receive data in response to the output clock signal.
10. The apparatus according to claim 1 , wherein selection of the delay element of the plurality of delay elements based on the associated delay value includes selecting the delay element having a lowest delay value.
11. An apparatus of an access point, the apparatus comprising:
one or more processors, configured to:
in a first mode:
identify a delay element of a plurality of delay elements based on an associated delay value; and
set an initial phase difference value to a phase difference value associated with the identified delay element; and
in a second mode:
initialize a digital phase-locked loop (DPLL) using the initial phase difference value; and
determine a phase error between a reference clock and a feedback clock based on the initial phase difference value; and
adjust an output clock signal based on the phase error.
12. The apparatus according to claim 11 , wherein the plurality of delay elements includes inverter circuits.
13. The apparatus according to claim 11 , wherein the DPLL includes:
a time-to-digital converter (TDC) to determine a delay value based on relative timing of the reference clock and the feedback clock using the plurality of delay elements; and
a lookup table to determine a phase estimation based on the delay value.
14. The apparatus according to claim 13 , wherein the DPLL further includes a digital phase detector (DPD) to determine a phase error based on a change in the phase estimation.
15. The apparatus according to claim 14 , wherein the DPLL further includes:
a loop filter to provide a frequency correction value based on the phase error; and
a controlled oscillator to provide the output clock signal.
16. The apparatus according to claim 11 , further comprising a physical layer to receive data in response to the output clock signal.
17. The apparatus according to claim 11 , wherein identification of the delay element of the plurality of delay elements based on the associated delay value includes identifying the delay element having a lowest delay value.
18. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors to initialize a digital phase lock loop of a wireless device by:
in a first mode:
measuring a respective delay value for a plurality of delay elements of a digital phase-locked loop (DPLL);
selecting a delay element of the plurality of delay elements based on a collective delay value between adjacent delay elements of the plurality of delay elements; and
setting an initial phase difference value to a phase difference value associated with the selected delay element; and
in a second mode:
initializing the DPLL using the initial phase difference value;
determining a phase error between a reference clock and a feedback clock based on the initial phase difference value; and
adjusting an output clock signal based on the phase error.
19. The medium according to claim 18 , wherein the plurality of delay elements are serially-coupled delay elements.
20. The medium according to claim 18 , wherein the instructions are further executable to:
compare a phase of the reference clock to a phase of the feedback clock to provide a delay value using the plurality of delay elements; and
look up a phase estimation value based on the delay value, wherein the phase error is based on the phase estimation value.
21. The medium according to claim 18 , wherein the instructions further cause the one or more processors to determine a phase error based on a change in the phase estimation value.
22. The medium according to claim 21 , wherein determining the phase error based on changes in the phase estimation value comprises:
calculating an instantaneous frequency based on a change in the estimated phase difference value;
comparing the instantaneous frequency to a desired frequency to determine a frequency error; and
integrating the frequency error to determine the phase error.
23. The medium according to claim 21 , wherein the instructions are further executable to:
provide a frequency correction value based on the phase error; and
provide the output clock signal based on the frequency correction value.
24. The medium according to claim 18 , wherein the instructions are further executable to select the delay element of the plurality of delay elements based on the associated delay value by selecting the delay element having a lowest delay value.