Mapping circuit and method for selecting cells of a multi core hybrid I/Q digital to analog converter

1. A method for selecting cells of a multi core hybrid I/Q digital to analog converter, comprising:

defining a first group of cores and a second group of cores for each data symbol to be transmitted;

selecting a first number of cells of the first group of cores for an I-code of the data symbol; and

selecting a second number of cells of the second group of cores for a Q-code of the data symbol,

wherein the cells for the I-code of the data symbol are selected only from the first group of cores and the cells for the Q-code of the data symbol are selected only from the second group of cores.

2. The method of claim 1 , further comprising:

using a first mapping algorithm to compute the first number of cells for the I-code;

using an identical second mapping algorithm to compute the second number of cells for the Q-code.

3. The method of claim 2 , further comprising:

selecting a fraction of the first number of cells within a first core of the first group of cores and the remaining cells of the first number of cells within a second core of the first group of cores.

4. The method of claim 1 , further comprising:

selecting the first number of cells of N cores by filling the cells of the cores of the first group in an ascending order starting from a first core; and

selecting the second number of cells by filling the cells of the cores of the second group in a descending order starting from an N-th core.

5. The method of claim 1 , further comprising:

selecting the second number of cells of N cores by filling the cells of the cores of the second group in an ascending order starting from core (N/2)+1; and

selecting the first number of cells filling the cells of the cores of the first group in a descending order starting from core N/2.

6. A mapping circuit for selecting cells of a multi core hybrid I/Q digital to analog converter, comprising:

a first sub-mapping circuit configured to define a first group of cores for each data symbol to be transmitted and to select a first number of cells of the first group of cores for an I-code of the data symbol; and

a second sub-mapping circuit configured to define a second group of cores for each data symbol and to select a second number of cells of the second group of cores for a Q-code of the data symbol,

wherein the cells for the I-code of the data symbol are selected only from the first group of cores and the cells for the Q-code of the data symbol are selected only from the second group of cores.

7. The mapping circuit of claim 6 , wherein the first sub-mapping circuit and the second sub-mapping circuit use identical logic to compute the first number of cells to select for the I-code and to compute the second number of cells to select for the Q-code.

8. The mapping circuit of claim 7 , wherein

N outputs of the first sub-mapping circuit for selecting the first number of cells of an N-core hybrid I/O digital to analog converter are coupled to I-code inputs of N-cores in an ascending order, and wherein

N outputs of the second sub-mapping circuit are coupled to Q-code inputs of the N-cores in a descending order.

9. The mapping circuit of claim 7 , wherein

N outputs of the second sub-mapping circuit for selecting the number of cells of an N-core hybrid I/O digital to analog converter are coupled to Q-code inputs of N-cores in an ascending order starting from core (N/2)+1, rolling over to the first core; and

N outputs of the first sub-mapping circuit are coupled to Q-code inputs of the N-cores in a descending order starting from core N/2, rolling over to N.

10. A multi core hybrid I/Q digital to analog converter, comprising

at least two hybrid digital to analog converter cores, each having an I-code input and a Q-code input; and

a mapping circuit for selecting cells of the multi core hybrid I/Q digital to analog converter according to claim 6 .

11. The multi core hybrid I/Q digital to analog converter of claim 10 , further comprising:

a signal combination circuit configured to combine I-code and Q-code outputs of each of the cores to generate an analog radio frequency signal.

12. A transmitter comprising a multi core hybrid I/Q digital to analog converter according to claim 10 .

13. The transmitter of claim 12 , further comprising a power amplifier coupled to an output of the multi core hybrid I/Q digital to analog converter.

14. The transmitter of claim 12 , further comprising a baseband signal processing path configured to calculate at least one I-code and at least one Q-code for a data symbol to be transmitted.