IP Library Granted Patent US 11,387,305
Granted Patent B2
US 11,387,305 · App. 16/475,471 · Granted Jul 12, 2022

Display substrate, display panel, display apparatus, and method of fabricating display substrate

Inventors: Shi Shu (Beijing, CN); Jiangnan Lu (Beijing, CN); Xing Zhang (Beijing, CN); Wei Liu (Beijing, CN); Zhengliang Li (Beijing, CN); Cuili Gai (Beijing, CN)
Assignee: BOE Technology Group Co., Ltd.
H01L27/3272H01L27/322H01L27/3269H01L51/56H01L2227/323
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,387,305
App. No.
16/475,471
Granted
Jul 12, 2022
Kind
B2
Abstract

The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a plurality of thin film transistors on the base substrate; and a plurality of semiconductor junctions configured to shield light from irradiating on active layers of the plurality of thin film transistors.

Claims (59)

1. A display substrate having a plurality of subpixel areas, comprising:

a base substrate;

a plurality of thin film transistors on the base substrate;

a plurality of semiconductor junctions configured to shield light from irradiating on active layers of the plurality of thin film transistors; and

a plurality of light emitting brightness value detectors including a plurality of second thin film transistors respectively electrically connected to a plurality of second semiconductor junctions;

wherein the plurality of second semiconductor junctions are respectively configured to detect light emitting brightness values in a plurality of subpixel areas of the display substrate, respectively.

2. The display substrate of claim 1 , wherein orthographic projections of at least some of the plurality of semiconductor junctions on the base substrate respectively cover orthographic projections of the active layers of the plurality of thin film transistors on the base substrate.

3. The display substrate of claim 1 , wherein at least some of the plurality of semiconductor junctions are respectively on a side of the active layers of the plurality of thin film transistors facing the base substrate.

4. The display substrate of claim 1 , further comprising a light shielding layer;

wherein the light shielding layer and the plurality of semiconductor junctions are configured to cooperatively shield light from irradiating on the active layers of the plurality of thin film transistors.

5. The display substrate of claim 4 , wherein an orthographic projection of the light shielding layer on the base substrate covers orthographic projections of the active layers of the plurality of thin film transistors on the base substrate; and

orthographic projections of at least some of the plurality of semiconductor junctions on the base substrate respectively cover orthographic projections of the active layers of the plurality of thin film transistors on the base substrate.

6. The display substrate of claim 1 , wherein the plurality of thin film transistors comprises an array of a plurality of first thin film transistors on the base substrate and respectively in the plurality of subpixel areas for driving light emission of the display substrate;

wherein the plurality of semiconductor junctions comprises a plurality of first semiconductor junctions respectively in the plurality of subpixel areas; and

orthographic projections of the plurality of first semiconductor junctions on the base substrate respectively covers orthographic projections of first active layers of the plurality of first thin film transistors on the base substrate.

7. The display substrate of claim 1 , further comprising a light shielding layer;

wherein the light shielding layer comprises a plurality of first light shielding blocks respective in the plurality of subpixel areas;

wherein the plurality of thin film transistors comprises an array of a plurality of first thin film transistors on the base substrate and respectively in the plurality of subpixel areas for driving light emission of the display substrate; and

orthographic projections of the plurality of first light shielding blocks on the base substrate respectively covers orthographic projections of first active layers of the plurality of first thin film transistors on the base substrate;

wherein the plurality of semiconductor junctions comprises a plurality of first semiconductor junctions respectively in the plurality of subpixel areas; and

the plurality of first semiconductor junctions and the plurality of first light shielding blocks are configured to cooperatively shield light from irradiating on the first active layers of the plurality of first thin film transistors.

8. The display substrate of claim 1 , further comprising a light shielding layer;

wherein orthographic projections of the plurality of second semiconductor junctions on the base substrate respectively covers orthographic projections of second active layers of the plurality of second thin film transistors on the base substrate;

the light shielding layer comprises a plurality of second light shielding blocks;

orthographic projections of the plurality of second light shielding blocks on the base substrate respectively covers orthographic projections of the second active layers of the plurality of second thin film transistors on the base substrate; and

the plurality of second semiconductor junctions and the plurality of second light shielding blocks are configured to cooperatively shield light from irradiating on the second active layers of the plurality of second thin film transistors.

9. The display substrate of claim 8 , wherein the plurality of second light shielding blocks are respectively electrically connected to source electrodes of the plurality of second thin film transistors, and are respectively electrically connected to the plurality of second semiconductor junctions.

10. The display substrate of claim 1 , wherein the plurality of semiconductor junctions further comprises a plurality of third semiconductor junctions; and

orthographic projections of the plurality of third semiconductor junctions on the base substrate respectively covers orthographic projections of second active layers of the plurality of second thin film transistors on the base substrate.

11. The display substrate of claim 10 , further comprising a light shielding layer;

wherein the light shielding layer comprises a plurality of third light shielding blocks;

orthographic projections of the plurality of third light shielding blocks on the base substrate respectively covers orthographic projections of the second active layers of the plurality of second thin film transistors on the base substrate; and

the plurality of third semiconductor junctions and the plurality of third light shielding blocks are configured to cooperatively shield light from irradiating on the second active layers of the plurality of second thin film transistors.

12. The display substrate of claim 1 , further comprising a light shielding layer;

wherein the plurality of semiconductor junctions further comprises a plurality of third semiconductor junctions;

orthographic projections of the plurality of third semiconductor junctions on the base substrate respectively covers orthographic projections of second active layers of the plurality of second thin film transistors on the base substrate;

the light shielding layer comprises a plurality of second light shielding blocks;

orthographic projections of the plurality of second light shielding blocks on the base substrate respectively covers orthographic projections of the second active layers of the plurality of second thin film transistors on the base substrate;

the orthographic projections of the plurality of second light shielding blocks on the base substrate at least partially respectively overlap with orthographic projections of the plurality of second semiconductor junctions on the base substrate;

the plurality of third semiconductor junctions and the plurality of second light shielding blocks are configured to cooperatively shield light from irradiating on the second active layers of the plurality of second thin film transistors.

13. The display substrate of claim 12 , wherein the plurality of second light shielding blocks are respectively electrically connected to source electrodes of the plurality of second thin film transistors, and are respectively electrically connected to the plurality of second semiconductor junctions.

14. The display substrate of claim 12 , wherein the plurality of second semiconductor junctions are respectively adjacent to the plurality of third semiconductor junctions;

each individual one of the plurality of second semiconductor junctions is spaced apart and insulated from a respective one of the plurality of third semiconductor junctions.

15. The display substrate of claim 14 , wherein each individual one of the plurality of second semiconductor junctions is spaced apart from the respective one of the plurality of third semiconductor junctions by a groove;

wherein the display substrate further comprises an insulating layer extending into the groove, thereby insulating each individual one of the plurality of second semiconductor junctions from the respective one of the plurality of third semiconductor junctions;

wherein a source electrode of each individual one of the plurality of second thin film transistors is electrically connected to a respective one of the plurality of second light shielding blocks through the groove;

the insulating layer insulates the source electrode from a respective one of the plurality of second semiconductor junctions; and

the plurality of second light shielding blocks are respectively electrically connected to source electrodes of the plurality of second thin film transistors, and are respectively electrically connected to the plurality of second semiconductor junctions.

16. The display substrate of claim 15 , wherein an orthographic projection of the source electrode of each individual one of the plurality of second thin film transistors on the base substrate is substantially non-overlapping with an orthographic projection of the respective one of the plurality of second semiconductor junctions on the base substrate.

17. The display substrate of claim 1 , further comprising a color filter;

wherein an orthographic projection of the color filter on the base substrate is substantially non-overlapping with orthographic projections of the plurality of second semiconductor junctions on the base substrate.

18. A display panel, comprising the display substrate of claim 1 .

19. A method of fabricating a display substrate having a plurality of subpixel areas, comprising:

forming a plurality of thin film transistors on a base substrate;

forming a light shielding layer;

forming a plurality of semiconductor junctions; and

forming a plurality of light emitting brightness value detectors including a plurality of second thin film transistors respectively electrically connected to a plurality of second semiconductor junctions;

wherein the light shielding layer and the plurality of semiconductor junctions are formed to cooperatively shield light from irradiating on active layers of the plurality of thin film transistors; and

the plurality of second semiconductor junctions are respectively configured to detect light emitting brightness values in a plurality of subpixel areas of the display substrate, respectively.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2023
From: BOE TECHNOLOGY GROUP CO., LTD.
To: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Reel/Frame 064397/0480 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: LU, JIANGNAN
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049758/0984 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: LIU, WEI
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049758/0987 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: SHU, SHI
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049758/0981 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: LI, ZHENGLIANG
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049758/0993 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: GAI, CUILI
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049759/0010 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: ZHANG, XING
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049758/0990 →
Continuity (1)
Related Publication 20210351256A1 · Nov 11, 2021