3D semiconductor device and structure
A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.
1. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source;
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors,
wherein at least of one of said plurality of overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and
memory control circuits,
wherein said memory control circuits are disposed at least partially directly underneath said plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above said plurality of overlaying horizontally-oriented memory transistors.
2. The 3D memory device according to claim 1 ,
wherein said plurality of overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist to enable said 3D memory device to operate at high speed.
3. The 3D memory device according to claim 1 , further comprising:
a third vertical pillar,
wherein said third vertical pillar and said second vertical pillar function as a source or a drain for a second plurality of overlaying horizontally-oriented memory transistors.
4. The 3D memory device according to claim 1 ,
wherein said memory control circuits are structured to provide a periodic memory refresh operation to said plurality of overlaying horizontally-oriented memory transistors.
5. The 3D memory device according to claim 1 ,
wherein said first vertical pillar comprises metal and does not comprise n+ type silicon.
6. The 3D memory device according to claim 1 ,
wherein said first vertical pillar and said second vertical pillar each comprise a filled cylinder shape.
7. The 3D memory device according to claim 1 ,
wherein each of said plurality of overlaying horizontally-oriented memory transistors comprises a unique channel region, and
wherein said unique channel regions are isolated from each other.
8. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source;
a second vertical pillar, said second vertical pillar comprises said transistor drain,
wherein said first vertical pillar and said second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors,
wherein said plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step,
wherein at least of one of said plurality of overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said plurality of overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist to enable said 3D memory device to operate at high speed.
9. The 3D memory device according to claim 8 , further comprising:
memory control circuits,
wherein said memory control circuits are structured to provide a periodic memory refresh operation to said plurality of overlaying horizontally-oriented memory transistors.
10. The 3D memory device according to claim 8 further comprising:
a third vertical pillar,
wherein said third vertical pillar and said second vertical pillar function as a source or a drain for a second plurality of overlaying horizontally-oriented memory transistors.
11. The 3D memory device according to claim 8 , further comprising:
a plurality of gate-lines,
wherein each of said plurality of gate-lines control one of said plurality overlaying horizontally-oriented memory transistors, and
wherein said plurality of gate-lines each comprise a built-in control transistor.
12. The 3D memory device according to claim 8 ,
wherein said first vertical pillar comprises metal and does not comprise n+ type silicon.
13. The 3D memory device according to claim 8 ,
wherein said first vertical pillar and said second vertical pillar each comprise a filled cylinder shape.
14. The 3D memory device according to claim 8 ,
wherein each of said plurality of overlaying horizontally-oriented memory transistors comprises a unique channel region, and
wherein said channel regions are isolated from each other.
15. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source;
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar function as a source or a drain for a first plurality of overlaying horizontally-oriented memory transistors,
wherein at least of one of said first plurality of overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said first plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and
a third vertical pillar,
wherein said third vertical pillar and said second vertical pillar function as a source or a drain for a second plurality of overlaying horizontally-oriented memory transistors.
16. The 3D memory device according to claim 15 ,
wherein said plurality of overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist to enable said 3D memory device to operate at high speed.
17. The 3D memory device according to claim 15 , further comprising:
memory control circuits,
wherein said memory control circuits are structured to provide a periodic memory refresh operation to said plurality of overlaying horizontally-oriented memory transistors.
18. The 3D memory device according to claim 15 ,
wherein said first vertical pillar comprises metal and does not comprise n+ type silicon.
19. The 3D memory device according to claim 15 ,
wherein said first vertical pillar and said second vertical pillar each comprise a filled cylinder shape.
20. The 3D memory device according to claim 15 ,
wherein each of said plurality of overlaying horizontally-oriented memory transistors comprises a unique channel region, and
wherein said channel regions are isolated from each other.