Sub-block wise interleaving for polar coding systems, procedures, and signaling
Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.
1. A wireless transmit/receive unit (WTRU) comprising:
a processor configured to:
generate a plurality of polar encoded bits, wherein the plurality of polar encoded bits is generated using a mother code length;
process the plurality of polar encoded bits into sub-blocks of equal size, wherein a size of each sub-block is a ratio of the mother code length and a number of the sub-blocks;
apply a sub-block wise interleaver pattern to the sub-blocks, wherein sub-blocks of a first subset of the sub-blocks change position, and sub-blocks of a second subset of the sub-blocks remain in an unchanged position; and
concatenate bits from each of the first subset of the sub-blocks and the second subset of the sub-blocks, wherein the concatenated bits are sequentially concatenated.
2. The WTRU of claim 1 , wherein a first part of the first subset of the sub-blocks and a first part of the second subset of the sub-blocks are consecutive and non-overlapping.
3. The WTRU of claim 1 , wherein a first part of the first subset of the sub-blocks comprises middle sub-blocks of the sub-blocks, and wherein a first part of the second subset of the sub-blocks is an even number of the sub-blocks, and wherein the first part of the second subset of the sub-blocks comprises an equal number of sub-blocks on each side of the first part of the first subset of the sub-blocks.
4. The WTRU of claim 3 , wherein a second part of the first subset of the sub-blocks is adjacent to the first part of the second subset of the sub-blocks.
5. The WTRU of claim 4 , wherein a second part of the second subset of the sub-blocks comprises sub-blocks other than the first part of the first subset of the sub-blocks, the first part of the second subset of the sub-blocks, and the seocnd part of the first subset of the sub-blocks, and wherein the second part of the second subset of the sub-blocks are adjacent to the second part of the first subset of the sub-blocks.
6. The WTRU of claim 1 , wherein the processor is further configured to store bits associated with each of the first subset of the sub-blocks and the second subset of the sub-blocks in a circular buffer.
7. The WTRU of claim 6 , wherein the processor is further configured to select a plurality of bits for transmission from the stored bits associated with each of the first subset of the sub-blocks and the second subset of the sub-blocks in the circular buffer, wherein the plurality of bits is selected based on a rate matching scheme, wherein the rate matching scheme is determined based on the mother code length, a rate matching output size, and a code rate, and wherein the rate matching scheme is one of a repetition scheme, a puncturing scheme, or a shortening scheme.
8. The WTRU of claim 7 , wherein the rate matching scheme is a repetition scheme, if rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme, if rate matching output size is less than the mother code length, and wherein selection between the shortening scheme and the puncturing scheme is based on a code rate.
9. The WTRU of claim 1 , wherein the interleaver pattern comprises: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, wherein the first subset of the sub-blocks comprises d 1 [3] through d 1 [4], and the second subset of the sub-blocks comprises d 1 [0] through d 2 [1], and d 1 [5] through d 1 [7].
10. The WTRU of claim 1 , wherein an order of bits within each sub-block of the first subset of the sub-blocks is maintained.
11. The WTRU of claim 1 , wherein the processor being configured to process the plurality of polar encoded bits into the sub-blocks of equal size comprises the processor being configured to divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner.
12. An interleaving method comprising:
generating a plurality of polar encoded bits, wherein the plurality of polar encoded bits is generated using a mother code length;
processing the plurality of polar encoded bits into sub-blocks of equal size, wherein a size of each sub-block is a ratio of the mother code length and a number of the sub-blocks;
applying a sub-block wise interleaver pattern to the sub-blocks, wherein sub-blocks of a first subset of the sub-blocks change position and sub-blocks of a second subset of the sub-blocks remain in an unchanged position; and
concatenating bits from each of the first subset of the sub-blocks and the second subset of the sub-blocks, wherein the concatenated bits are sequentially concatenated.
13. The method of claim 12 , wherein a first part of the first subset of the sub-blocks and a first part of the second subset of the sub-blocks are consecutive and non-overlapping.
14. The method of claim 12 , wherein a first part of the first subset of the sub-blocks comprises middle sub-blocks of the sub-blocks, and wherein a first part of the second subset of the sub-blocks is an even number of sub-blocks, and wherein the first part of the second subset of the sub-blocks comprises an equal number of sub-blocks on each side of the first part of the first subset of the sub-blocks, wherein a second part of the first subset of the sub-blocks is adjacent to the first part of the second subset of the sub-blocks, wherein a second part of the second subset of the sub-blocks comprises sub-blocks other than the first part of the first subset of the sub-blocks, the first part of the second subset of the sub-blocks, and the second part of the first subset of the sub-blocks, and wherein the second part of the second subset of the sub-blocks are adjacent to the second part of the first subset of the sub-blocks.
15. The method of claim 12 , comprising storing bits associated with the first subset of the sub-blocks and the second subset of the sub-blocks in a circular buffer.
16. The method of claim 15 , comprising selecting a plurality of bits for transmission from the stored bits asociated with each of the first subset of the sub-blocks and the second subset of the sub-blocks in the circular buffer, wherein the plurality of bits is selected based on a rate matching scheme, wherein the rate matching scheme is determined based on the mother code length, a rate matching output size, and a code rate, and wherein the rate matching scheme is one of a repetition scheme, a puncturing scheme, or a shortening scheme.
17. The method of claim 16 , wherein the rate matching scheme is a repetition scheme, if rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme, if rate matching output size is less than the mother code length, and wherein selection between the shortening scheme and the puncturing scheme is based on a code rate.
18. The method of claim 12 , wherein the interleaver pattern comprises: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, wherein the first subset of the sub-blocks comprises d 3 [2] through d 1 [4], and the second subset of the sub-blocks comprises d 1 [0] through d 2 [1], and d 1 [5] through d 1 [7].
19. The method of claim 12 , wherein an order of bits within each sub-block of the first subset of the sub-blocks is maintained.
20. The method of claim 12 , wherein processing the plurality of polar encoded bits into the sub-blocks of equal size comprises dividing the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner.