IP Library Granted Patent US 10,971,619
Granted Patent B2
US 10,971,619 · App. 16/502,492 · Granted Apr 6, 2021

Semiconductor device and manufacturing method of the same

Inventors: Hidemoto Tomita (Toyota, JP); Tomohiko Mori (Nagakute, JP)
Assignee: DENSO CORPORATION
H01L29/7802H01L21/0254H01L21/0274H01L21/02164H01L21/02389H01L21/02634H01L21/30625H01L21/31111H01L29/086H01L29/0865H01L29/0878H01L29/1083H01L29/1095H01L29/2003H01L29/36H01L29/41741H01L29/4916H01L29/66522H01L29/66712
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Quick Facts
Patent No.
US 10,971,619
App. No.
16/502,492
Granted
Apr 6, 2021
Kind
B2
Abstract

A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.

Claims (25)

1. A semiconductor device comprising:

a semiconductor layer;

a source electrode disposed above one main surface of the semiconductor layer;

a drain electrode disposed below another main surface of the semiconductor layer; and

an insulation gate section, wherein

the semiconductor layer comprises:

a drift region of a first conductivity type;

a JFET region of the first conductivity type disposed above the drift region;

a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and

a source region of the first conductivity type separated from the JFET region by the body region,

the insulation gate section is opposed to a portion of the body region that separates the JFET region and the source region,

an empty space is provided within the semiconductor layer, and

the drift region, the JFET region and the body region are exposed to the empty space.

2. The semiconductor device of claim 1 , wherein

as viewed in a direction orthogonal to the one main surface of the semiconductor layer, the empty space is located within an area where the body region exists.

3. The semiconductor device of claim 2 , wherein

a surface of the body region that is exposed to the empty space is a curved surface projecting toward the empty space.

4. The semiconductor device of claim 1 , wherein

as viewed in a direction orthogonal to the one main surface of the semiconductor layer, the empty space is located within an area where the JFET region exists.

5. The semiconductor device of claim 4 , wherein

a surface of the JFET region that is exposed to the empty space is a curved surface projecting toward the empty space.

6. The semiconductor device of claim 1 , wherein

a material of the semiconductor layer is a nitride semiconductor.

7. The semiconductor device of claim 1 , wherein

the empty space is configured to be in a vacuum state.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2019
From: TOMITA, HIDEMOTO; MORI, TOMOHIKO
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 049663/0093 →